3D IC技术与制造：香港肖的深度解析

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"3D IC Devices, Technologies, and Manufacturing" 是一本由Hong Xiao撰写的专业书籍，专注于探讨三维集成电路（3D IC）的设计、制造技术及其应用。这本书由SPIE（国际光学工程学会）于2016年出版，包含参考文献和索引，适用于对半导体行业，特别是3D IC领域感兴趣的读者。 3D IC技术是现代微电子学的一个关键进展，它通过在单个封装内堆叠多个芯片来实现更高的集成度和性能。这一技术对于解决摩尔定律所带来的挑战具有重要意义，因为它允许在有限的空间内增加更多的功能和处理能力，同时降低功耗和延迟。本书详细介绍了3D IC的各种器件结构，包括但不限于通过硅通孔（Through Silicon Via, TSV）、堆叠硅互联（Stacked Silicon Interconnect, SSI）以及芯片间的互连技术。TSV是一种关键的3D集成技术，它允许在不同层的芯片之间创建垂直的电气连接，从而极大地提高了数据传输速率和系统带宽。此外，书中还深入讨论了3D IC的制造工艺流程，包括材料选择、芯片键合、TSV形成、封装技术和良率优化等环节。这些工艺流程对于确保3D IC的可靠性和性能至关重要。作者可能还会涉及与热管理、机械应力、电气互连可靠性相关的挑战以及解决方案。 3D IC技术的应用广泛，涵盖了从数据中心的高速存储系统（如使用NAND闪存的3D堆叠存储芯片）到高性能计算、移动设备和物联网设备等多个领域。这种技术的实施不仅改变了传统集成电路的设计方式，也为未来电子系统的创新开辟了新的可能性。本书对于工程师、研究人员、学生以及任何想要了解半导体行业最新发展趋势的人来说都是宝贵的资源。通过阅读，读者将能深入理解3D IC的原理、设计方法、制造过程，以及它们如何推动电子行业的进步。 "3D IC Devices, Technologies, and Manufacturing" 为读者提供了一个全面的视角，深入剖析了3D集成电路的设计、制造工艺以及它们在当今科技领域的应用，是该领域的权威参考资料。

The channel length L and channel width W of the planar cell transistor,

RG transistor, and BWL transistor are shown in Figs. 1.7(a)–(c), respectively.

Note that L is the distance along the silicon surface between the source and

drain, the heavily n-type-doped silicon (marked N-Si in the figure). At the

same feature size, the RG transistor has the same channel width as the planar

transistor, which is the CD of the AA; however, it has a much longer channel

length. Furthermore, at the same geometry, the BWL transistor has the same

L as the RG transistor, with a larger W, because there is more silicon surface

exposed at the sides due to the deeper oxide etch in the BWL trench etch. The

edge of the P-Si channel side and its curved top in real BWL devices is not that

sharp—it is more like the shape of a saddle. Increasing the channel length can

help to reduce leakage and maintain the retention time. Increasing the channel

width can help to increase the drive current, and the BWL structure allows

increasing the channel width without increasing the feature size of the device.

Figure 1.8 shows a DRAM with a planar cell NMOS and stacked cylinder

capacitor. It represents the DRAM technology at 110 nm or earlier

technology nodes (described in detail in Chapter 14 of Xiao

), which used

three layers of aluminum metal interconnection. The so-called aluminum

metal layer in fact is a metal stack of Al-Cu (0.5% Cu) alloy bulk layers with

a Ti/TiN barrier layer underneath and a TiN anti-reflective coating (ARC) on

(a) (b) (c)

Figure 1.6 Evolution of the DRAM array cell NMOS: (a) planar, (b) RG, and (c) BWL.

Figure 1.7 3D illustration of the channel width and channel length of DRAM cell transistors:

(a) planar, (b) RG, and (c) BWL.

7Manufacturing Processes of 3D IC Devices

and before 3x-nm (i.e., 39-nm to 30-nm) technology nodes. Besides cell

transistors and capacitors, another major development of this period was the

introduction of copper metallization in 5x-nm DRAM. In comparison, logic

CMOS IC chips used copper metallization in interconnects since the 180-nm

technology node. There were two copper layers and one aluminum layer. The

top aluminum-alloy layer allowed the use of Al-Cu bond pads for the

standard gold wire bonding to keep the cost down. DRAM manufacturers are

very cost-sensitive, and DRAM fabrication-process technologies are cost

driven: two layers of copper can replace three layers of aluminum alloy, which

reduces the overall cost.

Figure 1.10(a) illustrates a BWL DRAM with a fully recessed cylinder

capacitor, and Fig. 1.10(b) is the 3D illustration of its memory cell structures.

Because the latter is based on the 6F

layout, it is quite different from Figs. 1.8(b)

and 1.9(b), which are based on the 8F

layout (these layouts are discussed in

Section 1.2.3). The BWL structure and 6F

layout have been widely used

in 3x-nm and 2x-nm DRAM technology nodes. There are three metal

interconnect layers: two copper layers and one aluminum-alloy layer.

If DRAM can be made with these three types of cell transistors with the

same single-patterning photolithography technology and the same capacitor

materials and structure, then the planar-cell transistor DRAM requires nine

masks, as shown in Fig. 1.11. The RG transistor DRAM adds a reversed WL

mask for the silicon etch to form a RG cell transistor; thus, it needs ten masks

in the array area, as illustrated in Fig. 1.12. The BWL DRAM uses one mask

for both well implantation and S/D implantation, and one mask to form the

RG and WL at the same time, while eliminating the SAC layer; thus, it only

needs seven masks (Fig. 1.13). Fewer masks means lower cost, which is one of

the most important reasons why BWL DRAM technology is used by all major

DRAM manufacturers. Note that Figs. 1.11–1.13 only show the mask layers

for the cell transistors and capacitors of the DRAM array area; they do not

include the masks required to make CMOS devices in the peripheral areas.

Ion implantation masks in cell transistor formation and well implantation

after active-area (AA) and S/D implantation after WL have a very large CD

and require less strict control of the CD and overlay. In a DRAM chip, the

feature sizes of peripheral circuits are much larger than the feature size of cell

devices. The feature size of peripheral devices is usually two generations

behind cell transistors. Advanced-technology nodes are processed separately

to avoid loading effects caused by pattern-density and pattern-size variations

on the processes such as photolithography, etch, CMP, etc. Although access

transistors used 3D devices for multiple generations, peripheral devices still

use planar MOSFET technology. Therefore, this book focuses on the

manufacturing processes in 3D devices in array areas.

10 Chapter 1

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