LPC111x/LPC11Cxx 用户手册 Rev.3

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"LPC111x_C1x User manual R3.pdf，这是一份关于NXP公司的LPC111x和LPC11Cxx系列微控制器的用户手册，修订版本为R3，发布日期为2011年1月14日。该手册主要涵盖基于ARMCortex-M0内核的微控制器，包括LPC1111、LPC1112、LPC1113、LPC1114以及LPC11C12和LPC11C14等多个型号。文档包含了产品介绍、功能描述、关键词、法律免责声明以及联系方式等信息。此外，手册还更新了部分内容，如添加了LPC11C22和LPC11C24的介绍，增加了对片上CAN收发器的描述，更新了系统滴答定时器的说明，指定了参考时钟作为时钟源，并对第12章进行了编辑更新。" LPC111x/LPC11Cxx系列是NXP半导体公司推出的基于ARMCortex-M0内核的微控制器，它们是针对低功耗、高性能嵌入式应用设计的。Cortex-M0是ARM公司的一种高效能、低功耗的处理器核心，适合于资源受限的嵌入式应用。LPC111x系列包括不同的存储器配置和外设集，例如LPC1111、LPC1112等，而LPC11Cxx系列则可能在功能和引脚排列上有所不同，如LPC11C12和LPC11C14。手册中的关键特性包括： 1. **ARMCortex-M0内核**：提供高效能的指令执行，优化的中断处理和低功耗模式。 2. **CAN收发器**：集成的CAN（Controller Area Network）模块，用于实现车辆网络通信和其他工业自动化系统中的高速通信。 3. **系统滴答定时器**：系统级的定时器，常用于调度任务和系统时间基准。 4. **参考时钟**：作为多个系统组件的时钟源，对于精确的时间管理和同步至关重要。 5. **单周期硬件乘法器**：在硬件层面完成乘法运算，极大地提高了计算速度。这些微控制器通常具备以下特点： - **丰富的外设接口**：如UART、SPI、I2C、GPIO等，满足各种外设连接需求。 - **多种低功耗模式**：如空闲、待机和停止模式，以适应不同应用场景的节能需求。 - **内置ADC（模拟数字转换器）**：用于处理模拟信号，将其转换为数字数据。 - **PWM（脉宽调制）**：用于电机控制、亮度调节等应用。 - **内存配置**：包含闪存和SRAM，用于程序存储和数据处理。用户手册会详细描述每个功能模块的工作原理、配置方法和编程接口，帮助开发者了解如何利用这些特性进行系统设计和软件开发。此外，手册还会提供样例代码和应用注意事项，以加速开发进程。对于嵌入式系统设计师来说，这份手册是理解和使用LPC111x/LPC11Cxx系列微控制器的重要参考资料。

User manual Rev. 3 — 14 January 2011 16 of 413

NXP Semiconductors

UM10398

Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)

3.5.3 System PLL control register

This register connects and enables the system PLL and configures the PLL multiplier and

divider values. The PLL accepts an input frequency from 10 MHz to 25 MHz from various

clock sources. The input frequency is multiplied up to a high frequency, then divided down

to provide the actual clock used by the CPU, peripherals, and memories. The PLL can

produce a clock up to the maximum allowed for the CPU.

3.5.4 System PLL status register

This register is a Read-only register and supplies the PLL lock status (see

Section 3.10.1

2 SSP1_RST_N SPI1 reset control 0

0 Resets the SPI1 peripheral.

1 SPI1 reset de-asserted.

3 CAN_RST_N C_CAN reset control 0

0 Resets the C_CAN peripheral.

1 C_CAN reset de-asserted.

31:4 - - Reserved 0x00

Table 8. Peripheral reset control register (PRESETCTRL, address 0x4004 8004) bit

description

Bit Symbol Value Description Reset

value

Table 9. System PLL control register (SYSPLLCTRL, address 0x4004 8008) bit description

Bit Symbol Value Description Reset

value

4:0 MSEL Feedback divider value. The division value M is the

programmed MSEL value + 1.

00000: Division ratio M = 1

11111: Division ratio M = 32.

0x000

6:5 PSEL Post divider ratio P. The division ratio is 2 × P. 0x00

0x0 P = 1

0x1 P = 2

0x2 P = 4

0x3 P = 8

31:7 - - Reserved. Do not write ones to reserved bits. 0x0

Table 10. System PLL status register (SYSPLLSTAT, address 0x4004 800C) bit description

Bit Symbol Value Description Reset

value

0 LOCK PLL lock status 0x0

0 PLL not locked

1 PLL locked

31:1 - - Reserved 0x00

User manual Rev. 3 — 14 January 2011 17 of 413

NXP Semiconductors

UM10398

Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)

3.5.5 System oscillator control register

This register configures the frequency range for the system oscillator.

3.5.6 Watchdog oscillator control register

This register configures the watchdog oscillator. The oscillator consists of an analog and a

digital part. The analog part contains the oscillator function and generates an analog clock

(Fclkana). With the digital part, the analog output clock (Fclkana) can be divided to the

required output clock frequency wdt_osc_clk. The analog output frequency (Fclkana) can

be adjusted with the FREQSEL bits between 500 kHz and 3.4 MHz. With the digital part

Fclkana will be divided (divider ratios = 2, 4,...,64) to wdt_osc_clk using the DIVSEL bits.

The output clock frequency of the watchdog oscillator can be calculated as

wdt_osc_clk =

Fclkana

(2 × (1 + DIVSEL))

= 7.8 kHz to 1.7 MHz (nominal values).

Remark: Any setting of the FREQSEL bits will yield a Fclkana value within ±40% of the

listed frequency value. The watchdog oscillator is the clock source with the lowest power

consumption. If accurate timing is required, use the IRC or system oscillator.

Remark: The frequency of the watchdog oscillator is undefined after reset. The watchdog

oscillator frequency must be programmed by writing to the WDTOSCCTRL register before

using the watchdog oscillator.

Table 11. System oscillator control register (SYSOSCCTRL, address 0x4004 8020) bit

description

Bit Symbol Value Description Reset

value

0 BYPASS Bypass system oscillator 0x0

0 Oscillator is not bypassed.

1 Bypass enabled. PLL input (sys_osc_clk) is fed

directly from the XTALIN and XTALOUT pins.

1 FREQRANGE Determines frequency range for Low-power

oscillator.

0x0

0 1 - 20 MHz frequency range.

1 15 - 25 MHz frequency range

31:2 - - Reserved 0x00

Table 12. Watchdog oscillator control register (WDTOSCCTRL, address 0x4004 8024) bit

description

Bit Symbol Value Description Reset

value

4:0 DIVSEL Select divider for Fclkana.

wdt_osc_clk = Fclkana/ (2 × (1 + DIVSEL))

00000: 2 × (1 + DIVSEL) = 2

00001: 2 × (1 + DIVSEL) = 4

11111: 2 × (1 + DIVSEL) = 64

8:5 FREQSEL Select watchdog oscillator analog output frequency

(Fclkana).

0x00

0x1 0.5 MHz

0x2 0.8 MHz

User manual Rev. 3 — 14 January 2011 20 of 413

NXP Semiconductors

UM10398

Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)

3.5.10 System PLL clock source update enable register

This register updates the clock source of the system PLL with the new input clock after the

SYSPLLCLKSEL register has been written to. In order for the update to take effect, first

write a zero to the SYSPLLUEN register and then write a one to SYSPLLUEN.

Remark: When switching clock sources, both clocks must be running before the clock

source is updated.

3.5.11 Main clock source select register

This register selects the main system clock which can be either any input to the system

PLL, the output from the system PLL (sys_pllclkout), or the watchdog or IRC oscillators

directly. The main system clock clocks the core, the peripherals, and the memories.

The MAINCLKUEN register (see Section 3.5.12

) must be toggled from LOW to HIGH for

the update to take effect.

Remark: When switching clock sources, both clocks must be running before the clock

source is updated.

Remark: When using the C_CAN controller with baudrates above 100 kbit/s, the system

oscillator must be selected.

3.5.12 Main clock source update enable register

This register updates the clock source of the main clock with the new input clock after the

MAINCLKSEL register has been written to. In order for the update to take effect, first write

a zero to the MAINCLKUEN register and then write a one to MAINCLKUEN.

Remark: When switching clock sources, both clocks must be running before the clock

source is updated.

Table 16. System PLL clock source update enable register (SYSPLLCLKUEN, address

0x4004 8044) bit description

Bit Symbol Value Description Reset value

0 ENA Enable system PLL clock source update 0x0

0 No change

1 Update clock source

31:1 - - Reserved 0x00

Table 17. Main clock source select register (MAINCLKSEL, address 0x4004 8070) bit

description

Bit Symbol Value Description Reset value

1:0 SEL Clock source for main clock 0x00

0x0 IRC oscillator

0x1 Input clock to system PLL

0x2 WDT oscillator

0x3 System PLL clock out

31:2 - - Reserved 0x00

剩余412页未读，继续阅读

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