USB 2.0 EHCI规范详解：2002年修订版

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USB Enhanced Host Controller Interface (EHCI) Specification 是针对通用串行总线 (USB) 的一个高级控制器接口规范，该规范旨在支持 USB 2.0 技术。发布日期为2002年3月12日，版本为1.0。这份文档提供的是一种“原样”提供，不附带任何形式的保证，包括但不限于商品质量保证、非侵权性、特定用途适用性或因建议、规格样本而产生的其他任何保证。 USB EHCI 规范定义了一个增强型主机控制器，它能提高USB设备间的通信效率和性能，尤其是在处理大量设备连接时。它允许主机控制器更有效地管理多个USB端口，通过改进的数据传输机制，减少了USB集线器（HUB）的级联层数，从而减少了延迟和提高了数据传输速度。在技术细节方面，EHCI规范着重于增强主机控制器的核心功能，如并发设备管理和并行数据传输。它引入了称为“端口状态机”的新概念，使得每个USB端口可以独立控制其连接设备的状态，从而实现了更高的并发处理能力。此外，它还支持USB 2.0的全速（1.5Mbps）和高速（480Mbps）模式，以及设备的唤醒和休眠管理。值得注意的是，这份规范强调了知识产权保护，指出它仅用于Intel产品的内部使用，并且没有授予任何形式的知识产权许可，除非明确表示。对于进一步的商业许可协议和使用要求，用户需要联系Intel获取详细信息。同时，Intel对其产品销售和使用的任何责任（包括侵犯专利权的责任）进行了免责声明，除了符合Intel销售条款的产品外。 USB EHCI Specification 是为了优化USB 2.0主机控制器设计的关键文档，对于理解如何实现高性能、高效能的USB设备管理和数据传输有着重要的价值。开发者和硬件制造商在设计和实施USB解决方案时，必须遵循这一规范，以确保与USB设备的兼容性和性能要求。

EHCI Revision 1.0 3/12/2002

USB 2.0

device connects, disconnects, performing device resets, manipulating port power and managing port power

management capabilities.

System software should provide an abstraction to the USB system software stack that allows the root hub

ports to be manipulated by the system as if they were ports on an external hub.

EHCI Revision 1.0 3/12/2002

USB 2.0 7

2. Register Interface

The Enhanced USB Host Controller contains two sets of software accessible hardware registersMemory-

mapped Host Controller Registers and optional PCI configuration registers. Note that the PCI configuration

registers are only needed for PCI devices that implement the Host Controller.

• PCI Configuration Registers (For PCI devices). In addition to the normal PCI header, power

management, and device-specific registers, two registers are needed in the PCI Configuration space to

support USB. The normal PCI header and device specific registers are beyond the scope of this

document (The CLASSC register is shown in this document). Note that HCD does not interact with the

PCI configuration space. This space is used only by the PCI enumerator to identify the USB Host

Controller, and assign the appropriate system resources.

• Memory-mapped USB Host Controller Registers. This block of registers is memory-mapped into

non-cacheable memory (see Figure 1-3). This memory space must begin on a DWord (32-bit) boundary.

This register space is divided into two sections: a set of read-only capability registers and a set of

read/write operational registers. Table 2-1, describes each register space.

Note that host controllers are not required to support exclusive-access mechanisms (such as PCI LOCK)

for accesses to the memory-mapped register space. Therefore, if software attempts exclusive-access

mechanisms to the host controller memory-mapped register space, the results are undefined.

Table 2-1. Enhanced Interface Register Sets

Offset Register Set Explanation

0 to N-1 Capability Registers

(Section 2.2)

The capability registers specify the limits, restrictions,

and capabilities of a host controller implementation.

These values are used as parameters to the host

controller driver.

N to

N+M-1

Operational Registers

(Section 2.3)

The operational registers are used by system

software to control and monitor the operational state

of the host controller.

The reserved bits defined in this revision of the specification may be allocated in later revisions. Software

should not assume reserved bits are always zero and should preserve these bits when writing to modifiable

registers. The following notation is used to describe register access attributes:

RO Read Only. If a register is read only, writes have no effect.

WO Write Only. If a register is write only, reads return a zero for all bit positions.

R/W Read/Write. A register with this attribute can be read and written. Note that individual bits in some

read/write registers may be read only.

R/WC Read/Write Clear. A register bit with this attribute can be read and written. However, a write of a 1

clears (sets to 0) the corresponding bit and a write of a 0 has no effect.

Registers in the auxiliary well are reset under different conditions than the registers in the core well. The

auxiliary well, memory-space registers are initialized to their default values in the following cases:

• initial power-up of the auxiliary power well, or

• a value of 1b in HCReset (see Section 2.3.1)

The core well, memory-space registers are initialized to their default values in the following cases:

• assertion of the system (core-well) hardware reset, or

• a value of 1b in HCReset, or

• transition from the PCI Power Management D3hot state to the D0 state

EHCI Revision 1.0 3/12/2002

8 USB 2.0

PCI configuration-space registers implemented in the auxiliary power well are reset under different

conditions than the registers in the core well. The auxiliary well, configuration-space registers are initialized

to their default value in the following case:

• initial power-up of the auxiliary power well

The core well PCI configuration-space registers are initialized to their default values in the following cases:

• assertion of the system (core-well) hardware reset, or

• transition from the PCI Power Management D3hot state to the D0 state

Exceptions to these reset conditions will be defined in the associated register section.

2.1 PCI Configuration Registers (USB)

Table 2-2 lists the PCI configuration space register for an EHCI controller. The following subsections

describe details about each set of registers defined.

Table 2-2. PCI Configuration Space Registers

Configuration

Offset

Mnemonic Register Power

Well

Access

00−08h  Register implementation as needed

for specific PCI device

Core 

09−0Bh CLASSC Class Code Core RO

0C−0Fh  Register implementation as needed

for specific PCI device

Core 

10−13h USBBASE Base Address to Memory-mapped

Host Controller Register Space

Core R/W

14−5Fh  Register implementation as needed

for specific PCI device

Core 

60h SBRN Serial Bus Release Number Core RO

61h FLADJ Frame Length Adjustment Register Aux R/W

62-63h PORTWAKECAP Port wake capabilities register

(OPTIONAL)

Aux R/W

64−FFh  Register implementation as needed

for specific PCI device

Core 

EECP+0h

USBLEGSUP USB Legacy Support EHCI Extended

Capability Register

Aux RO, R/W

EECP+4h USBLEGCTLSTS USB Legacy Support Control and

Status Register

Aux R/W, R/WC

The EECP field is in the HCCPARAMS register, see Section 2.2.4.

2.1.1 PWRMGT 



 PCI Power Management Interface

EHCI Host Controller implementations are required to implement the PCI Power Management registers as

defined in the PCI Bus Power Management Interface Specification Revision 1.1. Refer to Appendix A for

the EHCI operational requirements for PCI Power Management.

EHCI Revision 1.0 3/12/2002

USB 2.0 9

2.1.2 CLASSC 



 CLASS CODE REGISTER

Address Offset: 09−0Bh

Default Value: 0C0320h

Attribute: RO

Size: 24 bits

This register contains the device programming interface information related to the Sub-Class Code and Base

Class Code definition. This register also identifies the Base Class Code and the function sub-class in relation

to the Base Class Code.

Bit Description

23:16 Base Class Code (BASEC). 0Ch= Serial Bus controller.

15:8 Sub-Class Code (SCC). 03h=Universal Serial Bus Host Controller.

7:0 Programming Interface (PI). 20h=USB 2.0 Host Controller that conforms to this specification.

2.1.3 USBBASE 



 Register Space Base Address Register

Address Offset: 10−13h

Default Value: Implementation Dependent

Attribute: R/W

Size: 32 bits

This register contains the base address of the DWord-aligned memory-mapped host controller Registers. The

number of writable bits in this register determines the actual size of the required memory space window. The

minimum required is specified in this specification. Individual implementations may vary.

Bit Description

31:8 Base Address 



 R/W. Corresponds to memory address signals [31:8].

7:3 Reserved. 



 RO. This bits are read only and hardwired to zero.

2:1 Type. 



 RO. This field has two valid values:

Value Meaning

00b May only be mapped into 32-bit addressing space (Recommended).

10b May be mapped into 64-bit addressing space.

0 Reserved 



 RO. This bit is read only and hardwired to zero.

2.1.4 SBRN 



 Serial Bus Release Number Register

Address Offset: 60h

Default Value: See Description below

Attribute: RO

Size: 8 bits

This register contains the release of the Universal Serial Bus Specification with which this Universal Serial

Bus Host Controller module is compliant.

Bit Description

7:0 Serial Bus Specification Release Number. All other combinations are reserved.

Bits[7:0] Release Number

20h Release 2.0

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USB 2.0 EHCI规范详解：2002年修订版

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