Marvell Alaska 88E1111 2020版10/100/1000千兆以太网收发器规格
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Marvell Alaska系列88E1111是一款高度集成的10/100/1000兆比特超高速以太网收发器数据手册。该文档发布于2020年8月31日，版本号为MV-S100649-00Rev.M，属于公开文档类别。该芯片旨在提供高效、可靠的数据传输解决方案，适用于各种网络应用环境。
88E1111的主要特性包括：
1. 高速连接：支持10/100/1000Gbps的传输速率，能够处理大量数据流量，满足现代网络对高速、低延迟的需求。
2. 集成设计：作为一款单芯片解决方案，它集成了多个功能模块，如物理层接口、MAC（媒体访问控制）控制器、以及可能的PHY（物理层）控制器，简化了系统设计的复杂性。
3. 兼容性与标准支持：符合SGMII (Serial gigabit Media Independent Interface) 规范，这是一种广泛应用于高速以太网的接口标准，使得它能够无缝融入许多网络架构。
4. 可靠性与稳定性：虽然强调了“AS IS”提供，即不提供任何保证，但其作为一款工业级产品，它在设计时注重了高可靠性，能在各种环境下稳定运行，如数据中心、企业网络等。
5. 知识产权保护：Marvell及其许可方对其知识产权拥有严格保护，用户只能在合法使用Marvell产品的情况下参考此文档，未经授权的产品开发可能会侵犯专利或版权。
6. 责任与限制：用户自行负责根据提供的信息设计或构建产品，这意味着用户需要具备相应的专业知识，并理解可能存在的风险和局限性。
7. 适用范围：88E1111不是用于关键系统的理想选择，对于那些对安全性和法规遵从性有极高要求的应用，用户需额外评估和验证。
Marvell 88E1111是一款功能强大的以太网收发器，适用于追求高速度和效率的网络设备制造商，但用户在使用时需要充分理解其特性和限制条件，确保合规和系统的稳健性。
Doc. No. MV-S100649-00 Rev. M Copyright © 2020 Marvell
Page 16 Document Classification: Public August 31, 2020
Alaska 88E1111
Datasheet
Figure 37: PMOS Output Impedance (2.5V) Trend Line..................................................................................108
Figure 38: NMOS Output Impedance (2.5V) Trend Line .................................................................................108
Figure 39: Signal Reflections, using the 50 ohm Setting, 60 ohm line.............................................................109
Figure 40: Clean signal after manual calibration for the 60 ohm .....................................................................109
Figure 41: Single LED Connection...................................................................................................................111
Figure 42: Bi-Color LED Connection................................................................................................................111
3 Register Description.......................................................................................................................121
Figure 43: Register Map Summary .................................................................................................................122
4 Electrical Specifications ................................................................................................................ 183
Figure 44: CML I/Os.........................................................................................................................................197
Figure 45: AC connections (CML or LVDS receiver) or DC connection LVDS receiver ..................................199
Figure 46: DC connection to a CML receiver ...................................................................................................200
Figure 47: Input Differential Hysteresis............................................................................................................201
Figure 48: Reset Timing...................................................................................................................................203
Figure 49: XTAL1 Input Clock Timing ..............................................................................................................204
Figure 50: 125CLK Output Timing ...................................................................................................................205
Figure 51: GMII Transmit Timing .....................................................................................................................206
Figure 52: GMII Receive Timing ......................................................................................................................207
Figure 53: 10/100 Mbps Transmit Timing ........................................................................................................208
Figure 54: 10/100 Mbps Receive Timing .........................................................................................................209
Figure 55: TBI Transmit Timing .......................................................................................................................210
Figure 56: TBI Receive Timing ........................................................................................................................211
Figure 57: RGMII/RTBI Multiplexing and Timing .............................................................................................212
Figure 58: GTX_CLK Delay Timing - Register 20.1 = 0...................................................................................213
Figure 59: GTX_CLK Delay Timing - Register 20.1 = 1 (add delay)................................................................213
Figure 60: RGMII RX_CLK Delay Timing - Register 20.7 = 0..........................................................................214
Figure 61: RGMII RX_CLK Delay Timing - Register 20.7 = 1 (add delay).......................................................214
Figure 62: Serial Interface Rise and Fall Times...............................................................................................215
Figure 63: GMII/MII to 10/100/1000BASE-T Transmit Latency Timing............................................................217
Figure 64: 10/100/1000BASE-T to GMII/MII Receive Latency Timing.............................................................219
Figure 65: GMII to 1000BASE-X Transmit Latency Timing .............................................................................220
Figure 66: 1000BASE-X to GMII Receive Latency Timing ..............................................................................221
Figure 67: RGMII/MII to 10/100/1000BASE-T Transmit Latency Timing .........................................................222
Figure 68: 10/100/1000BASE-T to RGMII Receive Latency Timing ................................................................223
Figure 69: RGMII to 1000BASE-X Transmit Latency Timing ..........................................................................
.224
Figure 70: 1000BASE-X to RGMII Receive Latency Timing............................................................................225
Figure 71: TBI to 100BASE-T Transmit Latency Timing..................................................................................226
Figure 72: 1000BASE-T to TBI Receive Latency Timing .................................................................................227
Figure 73: RTBI to 1000BASE-T Transmit Latency Timing .............................................................................228
Figure 74: 1000BASE-T to RTBI Receive Latency Timing ..............................................................................228
Figure 75: SGMII to 10/100/1000BASE-T Transmit Latency Timing ...............................................................229
Figure 76: 10/100/1000BASE-T to SGMII Receive Latency Timing ................................................................230
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