e200z0 Power Architecture Core Reference Manual, Rev. 0
xvi Freescale Semiconductor
Figures
Figure
Number Title
Page
Number
5-5 e200 Interrupt Vector Addresses............................................................................................. 5-9
6-1 e200z0h Signal Groups ........................................................................................................... 6-3
6-2 e200z0 Signal Groups............................................................................................................. 6-4
6-3 Example External JTAG Register Design............................................................................. 6-32
6-4 Basic Read Transfers............................................................................................................. 6-35
6-5 Read Transfer with Wait-state............................................................................................... 6-37
6-6 Basic Write Transfers............................................................................................................ 6-38
6-7 Write Transfer with Wait-State ............................................................................................. 6-40
6-8 Single Cycle Read and Write Transfers ................................................................................ 6-41
6-9 Single Cycle Read and Write Transfers—2 .......................................................................... 6-42
6-10 Multi-Cycle Read and Write Transfers ................................................................................. 6-43
6-11 Multi-Cycle Read and Write Transfers—2 ........................................................................... 6-44
6-12 Misaligned Read Transfer..................................................................................................... 6-45
6-13 Misaligned Write Transfer .................................................................................................... 6-46
6-14 Misaligned Write, Single Cycle Read Transfer..................................................................... 6-47
6-15 Burst Read Transfer .............................................................................................................. 6-48
6-16 Burst Read with Wait-State Transfer..................................................................................... 6-49
6-17 Burst Write Transfer..............................................................................................................6-50
6-18 Burst Write with Wait-State Transfer.................................................................................... 6-51
6-19 Burst Read Transfers............................................................................................................. 6-52
6-20 Burst Read with Wait-State Transfer, Retraction.................................................................. 6-53
6-21 Burst Write Transfers, Single Beat Burst.............................................................................. 6-54
6-22 Read Transfer with Wait-State, Address Retraction ............................................................. 6-55
6-23 Burst Read with Wait-State Transfer, Retraction.................................................................. 6-56
6-24 Read and Write Transfers, Instr. Read Error Termination..................................................... 6-57
6-25 Data Read Error Termination................................................................................................ 6-58
6-26 Misaligned Write Error Termination..................................................................................... 6-59
6-27 Wakeup Control Signal (p_wakeup) ..................................................................................... 6-59
6-28 Interrupt Interface Input Signals ...........................................................................................6-60
6-29 e200 Interrupt Pending Operation......................................................................................... 6-61
6-30 e200z0h Interrupt Pending Operation................................................................................... 6-61
6-31 Interrupt Acknowledge Operation ........................................................................................ 6-62
6-32 Interrupt Acknowledge Operation—2 .................................................................................. 6-63
6-33 Time Base Input Timing........................................................................................................ 6-64
6-34 Test Clock Input Timing ....................................................................................................... 6-64
6-35 j_trst_b Timing...................................................................................................................... 6-64
6-36 Test Access Port Timing ....................................................................................................... 6-65
8-1 e200 Debug Resources............................................................................................................ 8-3
8-2 DBCR0 Register .....................................................................................................................8-9
8-3 DBCR1 Register ................................................................................................................... 8-11
8-4 DBCR2 Register ................................................................................................................... 8-13