Apollo2蓝版MCU数据手册：超低功耗特性与蓝牙集成

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"Apollo2 Blue MCU Data Sheet rev1p0.pdf" 该文档是关于Ambiq Micro公司的Apollo2 Blue微控制器的数据手册，主要介绍了Apollo2 Blue（AMA2B1KK-KLR）这一超低功耗微处理器家族的特点、功能和规格。Apollo2 Blue是一款基于ARMCortex-M4处理器的芯片，专为低功耗应用设计。 Apollo2 Blue的主要特点包括： 1. 极低的供电电流：在3.3V电压下，从闪存执行时电流小于10μA/MHz，从RAM执行时同样小于10μA/MHz。在3.3V电压下的深度睡眠模式下，带有RTC（实时时钟）且蓝牙关闭时，电流小于3μA。 2. 高性能：高达48MHz的时钟频率，内置浮点单元，支持更复杂的计算任务。还包括内存保护单元，确保程序执行的安全性。 3. 强大的外设接口：提供SPI、I2C、UART、I2S等通信接口，便于与各种传感器和其他设备连接。传感器支持包括磁力计、陀螺仪、加速度计以及心率监测器（HRM）。 4. 用户界面：可连接显示屏、触觉反馈模块（用于振动马达）和麦克风，同时支持按钮输入，方便用户交互。 5. 无线连接：集成蓝牙无线技术，符合BLE5标准，具有高灵敏度（-95dBm），发射功率范围从-40dBm到+5dBm，支持AES128位加密和空中更新（OTA）功能，能与其他2.4GHz无线技术共存，如WiFi和GPS。 Apollo2 Blue的典型系统配置可能包括一个BLE控制器，用于实现低功耗蓝牙通信，以及Ambiq Micro的Apollo2 MCU核心，共同构成了一个完整的系统级封装（System-in-Package, SiP）解决方案。总结来说，Apollo2 Blue是一款高度集成、低功耗的微控制器，适用于需要长时间运行和高效能计算的物联网、健康监测和便携式设备应用。其强大的外设支持和无线连接能力使其在智能穿戴设备、智能家居和物联网节点等领域具有广泛的应用潜力。

Apollo2 Blue Datasheet

DS-A2B-1p0 Page 16 of 552 2019 Ambiq Micro, Inc.

Table 137: BUCK2 Register ..................................................................................................... 103

Table 138: BUCK2 Register Bits ............................................................................................. 103

Table 139: BUCK3 Register ..................................................................................................... 104

Table 140: BUCK3 Register Bits ............................................................................................. 104

Table 141: LDOREG2 Register ................................................................................................ 105

Table 142: LDOREG2 Register Bits ........................................................................................ 105

Table 143: BODPORCTRL Register ....................................................................................... 106

Table 144: BODPORCTRL Register Bits ................................................................................ 107

Table 145: ADCCAL Register ................................................................................................. 107

Table 146: ADCCAL Register Bits .......................................................................................... 107

Table 147: ADCBATTLOAD Register .................................................................................... 108

Table 148: ADCBATTLOAD Register Bits ............................................................................ 108

Table 149: ADCREFCOMP Register ....................................................................................... 109

Table 150: ADCREFCOMP Register Bits ............................................................................... 109

Table 151: XTALCTRL Register ............................................................................................. 109

Table 152: XTALCTRL Register Bits ...................................................................................... 110

Table 153: XTALGENCTRL Register ..................................................................................... 111

Table 154: XTALGENCTRL Register Bits ............................................................................. 111

Table 155: BOOTLOADERLOW Register .............................................................................. 111

Table 156: BOOTLOADERLOW Register Bits ...................................................................... 111

Table 157: SHADOWVALID Register .................................................................................... 112

Table 158: SHADOWVALID Register Bits ............................................................................ 112

Table 159: ICODEFAULTADDR Register ............................................................................. 113

Table 160: ICODEFAULTADDR Register Bits ...................................................................... 113

Table 161: DCODEFAULTADDR Register ............................................................................ 113

Table 162: DCODEFAULTADDR Register Bits .................................................................... 113

Table 163: SYSFAULTADDR Register .................................................................................. 114

Table 164: SYSFAULTADDR Register Bits ........................................................................... 114

Table 165: FAULTSTATUS Register ...................................................................................... 114

Table 166: FAULTSTATUS Register Bits .............................................................................. 114

Table 167: FAULTCAPTUREEN Register ............................................................................. 115

Table 168: FAULTCAPTUREEN Register Bits ...................................................................... 115

Table 169: PMUENABLE Register ......................................................................................... 116

Table 170: PMUENABLE Register Bits .................................................................................. 116

Table 171: TPIUCTRL Register ............................................................................................... 116

Table 172: TPIUCTRL Register Bits ....................................................................................... 116

Table 173: CACHECTRL Register Map .................................................................................. 122

Table 174: CACHECFG Register ............................................................................................. 123

Table 175: CACHECFG Register Bits ..................................................................................... 123

Table 176: FLASHCFG Register ............................................................................................. 124

Table 177: FLASHCFG Register Bits ...................................................................................... 124

Table 178: CACHECTRL Register .......................................................................................... 125

Table 179: CACHECTRL Register Bits ................................................................................... 125

Table 180: NCR0START Register ........................................................................................... 126

Table 181: NCR0START Register Bits .................................................................................... 126

Table 182: NCR0END Register ............................................................................................... 127

Apollo2 Blue Datasheet

DS-A2B-1p0 Page 17 of 552 2019 Ambiq Micro, Inc.

Table 183: NCR0END Register Bits ........................................................................................ 127

Table 184: NCR1START Register ........................................................................................... 127

Table 185: NCR1START Register Bits .................................................................................... 127

Table 186: NCR1END Register ............................................................................................... 128

Table 187: NCR1END Register Bits ........................................................................................ 128

Table 188: DMON0 Register .................................................................................................... 128

Table 189: DMON0 Register Bits ............................................................................................ 129

Table 190: DMON1 Register .................................................................................................... 129

Table 191: DMON1 Register Bits ............................................................................................ 129

Table 192: DMON2 Register .................................................................................................... 129

Table 193: DMON2 Register Bits ............................................................................................ 130

Table 194: DMON3 Register .................................................................................................... 130

Table 195: DMON3 Register Bits ............................................................................................ 130

Table 196: IMON0 Register ..................................................................................................... 130

Table 197: IMON0 Register Bits .............................................................................................. 131

Table 198: IMON1 Register ..................................................................................................... 131

Table 199: IMON1 Register Bits .............................................................................................. 131

Table 200: IMON2 Register ..................................................................................................... 131

Table 201: IMON2 Register Bits .............................................................................................. 132

Table 202: IMON3 Register ..................................................................................................... 132

Table 203: IMON3 Register Bits .............................................................................................. 132

Table 204: Operating Modes .................................................................................................... 141

Table 205: Die-to-Die Interconnection Table ........................................................................... 144

Table 206: CMD Register for I2C Operations .......................................................................... 148

Table 207: CMD Register for SPI Operations .......................................................................... 148

Table 208: CMD Register Field Description ............................................................................ 148

Table 209: IOMSTR Register Map .......................................................................................... 162

Table 210: FIFO Register ......................................................................................................... 164

Table 211: FIFO Register Bits .................................................................................................. 164

Table 212: FIFOPTR Register .................................................................................................. 165

Table 213: FIFOPTR Register Bits .......................................................................................... 165

Table 214: TLNGTH Register .................................................................................................. 165

Table 215: TLNGTH Register Bits .......................................................................................... 166

Table 216: FIFOTHR Register ................................................................................................. 166

Table 217: FIFOTHR Register Bits .......................................................................................... 166

Table 218: CLKCFG Register .................................................................................................. 167

Table 219: CLKCFG Register Bits ........................................................................................... 167

Table 220: CMD Register ......................................................................................................... 168

Table 221: CMD Register Bits ................................................................................................. 168

Table 222: CMDRPT Register ................................................................................................. 169

Table 223: CMDRPT Register Bits .......................................................................................... 169

Table 224: STATUS Register ................................................................................................... 169

Table 225: STATUS Register Bits ........................................................................................... 169

Table 226: CFG Register .......................................................................................................... 170

Table 227: CFG Register Bits ................................................................................................... 170

Table 228: INTEN Register ...................................................................................................... 172

Apollo2 Blue Datasheet

DS-A2B-1p0 Page 18 of 552 2019 Ambiq Micro, Inc.

Table 229: INTEN Register Bits .............................................................................................. 172

Table 230: INTSTAT Register ................................................................................................. 173

Table 231: INTSTAT Register Bits .......................................................................................... 173

Table 232: INTCLR Register ................................................................................................... 174

Table 233: INTCLR Register Bits ............................................................................................ 175

Table 234: INTSET Register .................................................................................................... 176

Table 235: INTSET Register Bits ............................................................................................. 176

Table 236: Mapping of Direct Area Access Interrupts and Corresponding REGACCINTSTAT

Bits ............................................................................................................................................. 181

Table 237: I/O Interface Interrupt Control ................................................................................ 184

Table 238: IOSLAVE Register Map ........................................................................................ 192

Table 239: FIFOPTR Register .................................................................................................. 193

Table 240: FIFOPTR Register Bits .......................................................................................... 193

Table 241: FIFOCFG Register ................................................................................................. 193

Table 242: FIFOCFG Register Bits .......................................................................................... 194

Table 243: FIFOTHR Register ................................................................................................. 194

Table 244: FIFOTHR Register Bits .......................................................................................... 194

Table 245: FUPD Register ........................................................................................................ 195

Table 246: FUPD Register Bits ................................................................................................ 195

Table 247: FIFOCTR Register ................................................................................................. 195

Table 248: FIFOCTR Register Bits .......................................................................................... 195

Table 249: FIFOINC Register .................................................................................................. 196

Table 250: FIFOINC Register Bits ........................................................................................... 196

Table 251: CFG Register .......................................................................................................... 196

Table 252: CFG Register Bits ................................................................................................... 197

Table 253: PRENC Register ..................................................................................................... 197

Table 254: PRENC Register Bits .............................................................................................. 198

Table 255: IOINTCTL Register ............................................................................................... 198

Table 256: IOINTCTL Register Bits ........................................................................................ 198

Table 257: GENADD Register ................................................................................................. 199

Table 258: GENADD Register Bits .......................................................................................... 199

Table 259: INTEN Register ...................................................................................................... 199

Table 260: INTEN Register Bits .............................................................................................. 199

Table 261: INTSTAT Register ................................................................................................. 200

Table 262: INTSTAT Register Bits .......................................................................................... 200

Table 263: INTCLR Register ................................................................................................... 201

Table 264: INTCLR Register Bits ............................................................................................ 201

Table 265: INTSET Register .................................................................................................... 202

Table 266: INTSET Register Bits ............................................................................................. 202

Table 267: REGACCINTEN Register ...................................................................................... 203

Table 268: REGACCINTEN Register Bits .............................................................................. 203

Table 269: REGACCINTSTAT Register ................................................................................. 203

Table 270: REGACCINTSTAT Register Bits .......................................................................... 204

Table 271: REGACCINTCLR Register ................................................................................... 204

Table 272: REGACCINTCLR Register Bits ............................................................................ 204

Table 273: REGACCINTSET Register .................................................................................... 204

Apollo2 Blue Datasheet

DS-A2B-1p0 Page 19 of 552 2019 Ambiq Micro, Inc.

Table 274: REGACCINTSET Register Bits ............................................................................ 205

Table 275: HOST_IER Register ............................................................................................... 205

Table 276: HOST_IER Register Bits ........................................................................................ 205

Table 277: HOST_ISR Register ............................................................................................... 206

Table 278: HOST_ISR Register Bits ........................................................................................ 206

Table 279: HOST_WCR Register ............................................................................................ 206

Table 280: HOST_WCR Register Bits ..................................................................................... 207

Table 281: HOST_WCS Register ............................................................................................. 207

Table 282: HOST_WCS Register Bits ..................................................................................... 207

Table 283: FIFOCTRLO Register ............................................................................................ 208

Table 284: FIFOCTRLO Register Bits ..................................................................................... 208

Table 285: FIFOCTRUP Register ............................................................................................ 208

Table 286: FIFOCTRUP Register Bits ..................................................................................... 208

Table 287: FIFO Register ......................................................................................................... 209

Table 288: FIFO Register Bits .................................................................................................. 209

Table 289: PDM Clock Output Reference Table ...................................................................... 212

Table 290: PDM Operating Modes and Data Formats ............................................................. 213

Table 291: Digital Volume Control .......................................................................................... 214

Table 292: LPF Digital Filter Parameters ................................................................................. 215

Table 293: PDM Register Map ................................................................................................. 217

Table 294: PCFG Register ........................................................................................................ 218

Table 295: PCFG Register Bits ................................................................................................ 218

Table 296: VCFG Register ....................................................................................................... 220

Table 297: VCFG Register Bits ................................................................................................ 220

Table 298: FR Register ............................................................................................................. 221

Table 299: FR Register Bits ...................................................................................................... 221

Table 300: FRD Register .......................................................................................................... 222

Table 301: FRD Register Bits ................................................................................................... 222

Table 302: FLUSH Register ..................................................................................................... 222

Table 303: FLUSH Register Bits .............................................................................................. 222

Table 304: FTHR Register ........................................................................................................ 223

Table 305: FTHR Register Bits ................................................................................................ 223

Table 306: INTEN Register ...................................................................................................... 223

Table 307: INTEN Register Bits .............................................................................................. 223

Table 308: INTSTAT Register ................................................................................................. 224

Table 309: INTSTAT Register Bits .......................................................................................... 224

Table 310: INTCLR Register ................................................................................................... 225

Table 311: INTCLR Register Bits ............................................................................................ 225

Table 312: INTSET Register .................................................................................................... 225

Table 313: INTSET Register Bits ............................................................................................. 225

Table 314: Drive Strength Control Bits .................................................................................... 227

Table 315: Apollo2 Blue MCU Pad Function Mapping ........................................................... 228

Table 317: ................................................................................................................................ 229

Table 316: Pad Function Color and Symbol Code .................................................................. 230

Table 318: Special Pad Types ................................................................................................... 230

Table 319: I2C Pullup Resistor Selection ................................................................................. 231

Apollo2 Blue Datasheet

DS-A2B-1p0 Page 20 of 552 2019 Ambiq Micro, Inc.

Table 320: IO Master 0 I2C Configuration .............................................................................. 235

Table 321: IO Master 1 I2C Configuration .............................................................................. 235

Table 322: IO Master 2 I2C Configuration .............................................................................. 235

Table 323: IO Master 3 I2C Configuration .............................................................................. 236

Table 324: IO Master 4 I2C Configuration .............................................................................. 236

Table 325: IO Master 5 I2C Configuration .............................................................................. 236

Table 326: IO Master 0 4-wire SPI Configuration ................................................................... 236

Table 328: IO Master 1 4-wire SPI Configuration ................................................................... 238

Table 329: IO Master 1 4-wire SPI nCE Configuration ........................................................... 238

Table 327: IO Master 0 4-wire SPI nCE Configuration ........................................................... 238

Table 330: IO Master 2 4-wire SPI Configuration ................................................................... 239

Table 331: IO Master 2 4-wire SPI nCE Configuration ........................................................... 239

Table 332: IO Master 3 4-wire SPI Configuration ................................................................... 240

Table 333: IO Master 3 4-wire SPI nCE Configuration ........................................................... 240

Table 334: IO Master 4 4-wire SPI Configuration ................................................................... 241

Table 335: IO Master 4 4-wire SPI nCE Configuration ........................................................... 241

Table 336: IO Master 5 4-wire SPI Configuration ................................................................... 241

Table 337: IO Master 5 4-wire SPI nCE Configuration ........................................................... 242

Table 338: IO Master 0 3-wire SPI Configuration ................................................................... 242

Table 339: IO Master 1 3-wire SPI Configuration ................................................................... 242

Table 340: IO Master 2 3-wire SPI Configuration ................................................................... 243

Table 341: IO Master 3 3-wire SPI Configuration ................................................................... 243

Table 342: IO Master 4 3-wire SPI Configuration ................................................................... 243

Table 343: IO Master 5 3-wire SPI Configuration ................................................................... 244

Table 344: IO Slave I2C Configuration .................................................................................... 244

Table 345: IO Slave 4-wire SPI Configuration ........................................................................ 244

Table 346: IO Slave 3-wire SPI Configuration ........................................................................ 245

Table 347: I2C Loopback ......................................................................................................... 245

Table 348: 3-wire SPI Loopback .............................................................................................. 245

Table 349: 4-wire SPI Loopback .............................................................................................. 246

Table 350: Counter/Timer Pad Configuration .......................................................................... 247

Table 352: UART0 RX Configuration ..................................................................................... 249

Table 353: UART0 RTS Configuration .................................................................................... 249

Table 351: UART0 TX Configuration ...................................................................................... 249

Table 354: UART0 CTS Configuration .................................................................................... 250

Table 357: UART1 RTS Configuration .................................................................................... 251

Table 358: UART1 CTS Configuration .................................................................................... 251

Table 355: UART1 TX Configuration ...................................................................................... 251

Table 356: UART1 RX Configuration ..................................................................................... 251

Table 360: PDM DATA Configuration .................................................................................... 253

Table 361: I2S BCLK Configuration ........................................................................................ 253

Table 362: I2S WCLK Configuration ...................................................................................... 253

Table 363: I2S DAT Configuration ......................................................................................... 253

Table 359: PDM CLK Configuration ....................................................................................... 253

Table 364: CLKOUT Configuration ......................................................................................... 254

Table 365: 32kHz CLKOUT Configuration ............................................................................. 254

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