Apollo2 Blue Datasheet
DS-A2B-1p0 Page 17 of 552 2019 Ambiq Micro, Inc.
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Table 183: NCR0END Register Bits ........................................................................................ 127
Table 184: NCR1START Register ........................................................................................... 127
Table 185: NCR1START Register Bits .................................................................................... 127
Table 186: NCR1END Register ............................................................................................... 128
Table 187: NCR1END Register Bits ........................................................................................ 128
Table 188: DMON0 Register .................................................................................................... 128
Table 189: DMON0 Register Bits ............................................................................................ 129
Table 190: DMON1 Register .................................................................................................... 129
Table 191: DMON1 Register Bits ............................................................................................ 129
Table 192: DMON2 Register .................................................................................................... 129
Table 193: DMON2 Register Bits ............................................................................................ 130
Table 194: DMON3 Register .................................................................................................... 130
Table 195: DMON3 Register Bits ............................................................................................ 130
Table 196: IMON0 Register ..................................................................................................... 130
Table 197: IMON0 Register Bits .............................................................................................. 131
Table 198: IMON1 Register ..................................................................................................... 131
Table 199: IMON1 Register Bits .............................................................................................. 131
Table 200: IMON2 Register ..................................................................................................... 131
Table 201: IMON2 Register Bits .............................................................................................. 132
Table 202: IMON3 Register ..................................................................................................... 132
Table 203: IMON3 Register Bits .............................................................................................. 132
Table 204: Operating Modes .................................................................................................... 141
Table 205: Die-to-Die Interconnection Table ........................................................................... 144
Table 206: CMD Register for I2C Operations .......................................................................... 148
Table 207: CMD Register for SPI Operations .......................................................................... 148
Table 208: CMD Register Field Description ............................................................................ 148
Table 209: IOMSTR Register Map .......................................................................................... 162
Table 210: FIFO Register ......................................................................................................... 164
Table 211: FIFO Register Bits .................................................................................................. 164
Table 212: FIFOPTR Register .................................................................................................. 165
Table 213: FIFOPTR Register Bits .......................................................................................... 165
Table 214: TLNGTH Register .................................................................................................. 165
Table 215: TLNGTH Register Bits .......................................................................................... 166
Table 216: FIFOTHR Register ................................................................................................. 166
Table 217: FIFOTHR Register Bits .......................................................................................... 166
Table 218: CLKCFG Register .................................................................................................. 167
Table 219: CLKCFG Register Bits ........................................................................................... 167
Table 220: CMD Register ......................................................................................................... 168
Table 221: CMD Register Bits ................................................................................................. 168
Table 222: CMDRPT Register ................................................................................................. 169
Table 223: CMDRPT Register Bits .......................................................................................... 169
Table 224: STATUS Register ................................................................................................... 169
Table 225: STATUS Register Bits ........................................................................................... 169
Table 226: CFG Register .......................................................................................................... 170
Table 227: CFG Register Bits ................................................................................................... 170
Table 228: INTEN Register ...................................................................................................... 172