HOLTIC HI-613x系列：3.3V MIL-STD-1553B 多功能接口芯片

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1553B

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"HI6130是Holt Integrated Circuits公司的一款符合MIL-STD-1553B和MIL-STD-1760标准的3.3V CMOS集成电路，支持单功能或多功能接口，可用于连接主机处理器与MIL-STD-1553B总线。该器件集成了Bus Controller (BC)、Bus Monitor Terminal (MT)以及两个独立的Remote Terminals (RTs)，可同时启用这些功能进行并发操作。" 正文： Holt Integrated Circuits的HI-6130系列芯片是针对军事和航空航天应用设计的，主要遵循MIL-STD-1553B协议，这是一种在军事系统中广泛使用的串行通信协议。该设备的独特之处在于它在一个单一的芯片上集成了Bus Controller、Bus Monitor Terminal以及两个Remote Terminals，这使得它可以灵活地处理多种MIL-STD-1553B总线任务，包括控制、监控和远程终端功能。 HI-6130芯片的工作原理是通过共享的片上双总线收发器和外部变压器与MIL-STD-1553B总线进行通信。这种设计减少了外部组件的需求，提高了系统的可靠性和紧凑性。用户可以根据应用需求分配64KB的片上静态RAM来满足不同终端的需求。 HI-6130系列提供了两种不同的主机接口选项：HI-6130采用16位并行总线，适用于需要高速数据传输的应用；而HI-6131则通过4线Serial Peripheral Interface (SPI)与主机通信，适合那些空间有限或对功耗有严格要求的系统。对于需要同时使用这两种接口的场合，HI-6132提供了16位并行总线和SPI的组合，封装在一个15x15mm的密封陶瓷封装中，以确保在恶劣环境下的稳定性。封装方面，HI-6130采用100引脚塑料四方扁平封装(PQFP)，HI-6131则可能有更适合小型化应用的封装形式，而HI-6132则结合了两种接口，封装在更小的尺寸内。 HI-6130系列集成电路是为满足军事和航空航天系统对MIL-STD-1553B协议高效、灵活且可靠的实现而设计的。其多样化的接口选择和集成的终端功能使其能够适应广泛的系统需求，确保在关键任务应用中的稳定性能。

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HI-6130, HI-6131

HOLT INTEGRATED CIRCUITS

2. FEATURE OVERVIEW

2.1. Bus Controller Operation

The HI-613x is congurable to operate as a Bus Controller

(BC). The BC is a programmable message-sequencing

device for control in MIL-STD-1553B applications.

Programmed using a set of 28 instruction op codes,

the BC greatly reduces the host’s processing workload.

The BC can optionally use a 16- or a 32-bit time base,

clocked from a choice of six internally generated clocks,

or an external time base clock. Special BC op codes

manage all 32-bit time base functions.

The programmable HI-613x Bus Controller autonomously

supports multi-frame message scheduling, message

retry schemes, storage of message data, asynchronous

message insertion and status /error reporting to the host

processor.

2.2. Remote Terminal Operation

The HI-613x is congurable to operate one as or two

Remote Terminals. The RTs are modeled after the popular

Holt HI-6120/21 Remote Terminal. The two Remote

Terminals operate with independent characteristics,

each RT having fully separate RAM structures (e.g.,

descriptor and illegal command tables) and independent

conguration and status registers. RAM bu󰀨er options

include single, double and 2 circular bu󰀨er choices. The

two RTs can be reset and reinitialized independently.

The full benet of two autonomous RTs is achieved

while using the same complexity and circuit board area

as a single Remote Terminal.

2.3. Monitor Terminal Operation

Message commands, terminal responses and message

data are stored in internal RAM, using one of two

possible modes. Simple Monitor Terminal (SMT) and

IRIG Monitor Terminal (IMT) Modes are targeted for

di󰀨erent applications. When operating in SMT mode, the

MT records commands and data separately. The SMT

can utilize 16- or 48-bit time tags with a range of clocking

options.

The IMT mode operation is designed to meet data

recording requirements of Telemetry Standard RCC

Document 106-07, Chapter 10. This “IRIG 106 Chapter

10” data recorder uses 48-bit relative time stamping,

having 10MHz (100ns) resolution. Message time stamps

occur at one of three selectable message progress

points. Several error handling schemes are available.

Bus Monitor interrupts notify the host when circular bu󰀨er

rollover occurs, or when a user-programmed bu󰀨er level

has been reached. The IMT stores message records

in the assigned bu󰀨er using IRIG 106 “packet body”

format. The device can optionally generate complete

IRIG 106 packets, including full packet headers and

trailers meeting IRIG 106 Chapter 10 requirements.

2.4. Interrupts

Host interrupts can originate from device hardware or

any of the enabled terminal devices (up to 4 devices).

A circular 64-word Interrupt Log Bu󰀨er retains interrupt

information from the last 32 interrupts, while the

hardware maintains a count of occurring interrupts since

the previous host bu󰀨er service.

Hardware-assisted interrupt decoding provides quick

identication of the interrupt source by terminal device:

BC, MT, RT1, RT2 or hardware. When a hardware

interrupt occurs (e.g., Bus A Loopback Failure), a

Pending Hardware Interrupt register bit explicitly

identies the interrupt source. For interrupts from BC,

MT or RT, the three low-order bits in the same register

identify the specic interrupt register (or registers) with

pending interrupts: that is, the BC, MT or RT Pending

Interrupt registers.

2.5. Reset and Initialization

After hardware Master Reset, there are two HI-

613x initialization methods: host initialization or self-

initialization from external serial EEPROM. For host

initialization, the host processor uses its bus interface

or 4-wire SPI to load HI-613x registers and initialize

tables, data bu󰀨ers, etc. in internal static RAM. For self-

initialization, the device uses setup information contained

within an external serial EEPROM. A dedicated 4-wire

SPI port reads data from the serial EEPROM and writes

it to registers and RAM. Error checking is performed,

looking for data mismatch or an EEPROM checksum

error.

Individual 1553 terminal devices (BC, MT, RT1 or RT2)

can be re-initialized from the serial EEPROM by writing

to the Reset Initialization Register.

HI-6130, HI-6131

HOLT INTEGRATED CIRCUITS

3. PIN DESCRIPTIONS

Table 1. Common pins (Apply to all devices)

Pin Function Description

MCLK

Input

50kΩ pull-down

Master clock input, 50.0MHz +/-100 ppm.

TTCLK

MTTCLK

Inputs

50kΩ pull-down

Optional clock input for BC time base and RT time tag counters.

Optional clock input for the MT time tag counter.

Each function (BC, MT, RT1, RT2) has an independent time tag counter. The BC

and RT counters share a common clock, selectable from internally generated

frequencies, or an external clock input. The MT time tag counter has its own

external or internal clock source.

Input

50kΩ pull-up

Master reset, active low. A minimum pulsewidth of 50ns and two rising clock

edges are required following the rising edge of MR to complete reset.

The host can also assert software reset by setting bits in the Master Status &

Reset register.

TXINHA

TXINHB

Inputs

50kΩ pull-down

Transmit inhibit inputs for Bus A and Bus B, active high. These two inputs are

logically ORed with the pair of corresponding bits in the Master Conguration

all enabled 1553 devices.

MTSTOFF

Input

50kΩ pull-down

Memory test disable, active high. When this pin is low, the device performs a

memory test on the entire RAM after rising edge on the MR reset pin. When

this pin is high, RAM testing is skipped, resulting in a faster reset process. For

further information, refer to Section 23.

AUTOEN

Input

50kΩ pull-down

Auto-Initialize Enable, active high. If this pin is high at rising edge on MR reset

pin, self-initialization proceeds, copying conguration data to registers and RAM

from an external serial EEPROM via a dedicated EEPROM SPl port. Refer to

Section 23.

READY Output

This pin is low when auto-initialization or built-in test is in process. The host

cannot read or write device RAM or registers when pin state is low; reads to

any address return the value in the Master Status & Reset register. When the

AUTOEN pin is low at Master Reset, the host can congure device RAM and

registers after READY goes high.

ACTIVE Output

This pin is high while an enabled BC or RT in the device is processing a 1553

message. The IMTA bit 1 in Master Conguration Register 0x0000 logically-

ORs bus monitor (MT) activity as well.

ECS

ESCK

MOSI

MISO

Output

Input

50kΩ pull-down

Dedicated 4-wire Serial Peripheral Interface (SPI) for connection to an optional

external EEPROM used for automatic self-initialization when AUTOEN is high

at Master Reset.

EECOPY

Input

50kΩ pull-down

EEPROM Copy, active high. Asserting this input initiates RAM and register copy

into serial EEPROM used for auto-initialization. Refer to Section 23.

HI-6130, HI-6131

HOLT INTEGRATED CIRCUITS

Pin Function Description

BCENA

Input

50kΩ pull-down

Bus Controller Enable input, active high.

BCTRIG

Input

50kΩ pull-down

BC Trigger input, active high. Used in conjunction with certain BC instructions.

MTRUN

Input

50kΩ pull-down

Monitor Run / Stop input, active high. This input starts/stops MT data recording.

Upon going low, the MT stops when the current message is completed.

RT1ENA

RT2ENA

Inputs

50kΩ pull-down

RT1 and RT2 enable input pins, active high. These inputs are logically ANDed

with the corresponding RT1ENA and RT2ENA bits in Master Conguration

Tables, and must be high when the Master Conguration Register RT1STEX or

RT2STEX start execution bits are asserted to begin RT1 or RT2 operation.

RT1LOCK

RT2LOCK

Inputs

50kΩ pull-down

Pin states are latched to the Lock bit in the RTx Operational Status register

when rising edge occurs on the MR pin. If status register Lock bit is high, the

host cannot overwrite the terminal address in the same register. If status register

Lock bit is low, the host can overwrite the terminal address and parity (and the

Lock bit) in the RTx Operational Status register.

RT1MC8

RT2MC8

Outputs

Remote Terminal “Reset RT” mode command (MC8) received. This active low

output is asserted at Status Word completion when RT1 or RT2 received a

“Reset Remote Terminal” mode code command. The minimum output pulse

width is 100ns, una󰀨ected by MR assertion.

RT1SSF

RT2SSF

Inputs

50kΩ pull-down

RT Subsystem Fail input, active high. When this input is high, the selected RT1

or RT2 sets the Subsystem Fail ag in its transmit status word. This input is

logically-ORed with the SSYSF bit in the terminal’s RT1 or RT2 1553 Status

Word Bits register.

MTPKRDY Output

Monitor Packet Ready output, active high. This pin is asserted when a message

data packet is complete, as dened by the various MT conguration registers

(maximum word or message count, maximum packet time, etc.) Assertion of

this bit indicates the MT has stopped.

IRQ Output

Interrupt request, active low. This pin is asserted each time an enabled interrupt

event occurs. This signal is programmed as a brief low-going pulse output or

as a level output by the INTSEL bit in the Master Conguration Register. If level

output is selected, IRQ stays low until the host acknowledges IRQ by pulsing a

rising edge at the ACKIRQ pin.

ACKIRQ

Input

50kΩ pull-down

Interrupt Acknowledge, active high. This input is only used when the INTSEL bit

in the RT Conguration Register is high, enabling level interrupt assertion for the

IRQ pin. When interrupt assertion causes the IRQ pin to go low, a high-going

pulse on ACKIRQ (250ns minimum duration) clears the IRQ output to logic 1.

RT1A4:0

RT1AP

RT2A4:0

RT2AP

Inputs

50kΩ pull-ups

Remote terminal address bits 4 - 0, and parity bit for RT1 and RT2. The RTAP

pin provides odd parity for the address on pins RTA4:0.

The terminal address and parity pin levels are latched into the respective RT

Operational Status Registers when rising edge occurs on the MR pin. The RT

Operational Status Register value (not these pins) reects the active terminal

address. The host can overwrite the RT Operational Status register address

value only when the register Lock bit is reset.

HI-6130, HI-6131

HOLT INTEGRATED CIRCUITS

Pin Function Description

BENDI

Input

50kΩ pull-up

Big Endian Conguration Pin

The BENDI pin works in conjunction with the A0 and BWID pins to determine the

“endianness” or byte order of 16-bit word transfers to the HI-6130. Table 3 below

summarizes the interoperability of the three pins.

When using the HI-6131, this pin controls the byte order of transferred 16-bit

data following the SPI command. When BENDI is low, “little endian” is chosen;

the low order byte (bits 7:0) is transacted on the SPI before the high order byte

(bits 15:8). When BENDI is high, “big endian” is chosen and the high order byte

is transacted on the SPI before the low order byte.

RAMEDC

Input

50kΩ pull-down

RAM EDC (Error Detection / Correction) enable.

When pin is low, device operates with 32K word RAM address space, EDC

disabled. When pin is high, device operates with 24K word RAM address space

with EDC enabled. All single-bit RAM read errors are automatically corrected.

The corrected errors and uncorrectable multi-bit RAM read errors can generate

separate, optional interrupts.

TEST

Input

50kΩ pull-down

Test enable input. The host asserts this pin to perform RAM self-test and loop-

back tests.

MODE

Input

50kΩ pull-up

Pin used for factory test. Do not connect.

VCC

VCCP

GND

Power Supply 3.3VDC power supply for logic and bus transceiver.

BUSA

Analog

Bi-directional Bus A interface to external MIL-STD-1553 isolation transformer.

Observe positive / negative polarity.

BUSB

Analog

Bi-directional Bus B interface to external MIL-STD-1553 isolation transformer.

Observe positive / negative polarity.

Table 2. Pins that apply to HI-6130 or HI-6132 only (Host parallel bus interface)

Pin Function Description

Input

50kΩ pull-up

Chip Enable, active low. When asserted, this pin enables host read or write

accesses to device RAM or registers using the host’s parallel bus interface. This

pin is normally connected to a Chip Select output from the host’s bus interface.

D15:0

In / Out

50kΩ pull-down

Tri-state data bus for host read/write operations upon registers and shared

RAM. All bus read/write operations transact 16 bit words, but bus width can be

congured for 8 or 16 bits. For 8-bit bus width, pins D15:8 are not connected.

Sixteen-bit words are transacted over an 8-bit bus as a pair of byte operations,

with data presented sequentially on pins D7:0. For compatibility with di󰀨erent

host processors, the BENDI input determines whether the low order byte is

transferred before the high order byte, or vice versa. See Table 3.

HI-6130, HI-6131

HOLT INTEGRATED CIRCUITS

Pin Function Description

A15:1

A0 / LB

Input

50kΩ pull-up

Address bus for host read/write operations upon registers and shared RAM.

When using 16-bit bus width, address bit A0 / (LB) from the host is not used. For

8-bit bus width, A0 is used to indicate which byte of the 16-bit word is currently

being transferred (MSB or LSB). The logic sense of A0 is controlled by the

BENDI input (see BENDI pin description and Table 3 below).

BWID

Input

50kΩ pull-up

Conguration pin for host bus width. High selects 16-bit bus width, low selects

8-bit bus width.

BTYPE

Input

50kΩ pull-up

Conguration pin for host bus read/write control signal style. High selects “Intel

style” using separate read strobe OE (output enable) and write strobe WE. Low

selects “Motorola style” using single active-low read/write strobe STR and read/

write select signal, R/W.

R/W / WE

Input

50kΩ pull-up

Read/write direction signal R/W when BTYPE pin is low.

Active-low Write Enable WE when BTYPE pin is high.

Used for host read or write accesses to device RAM or registers. This pin or the

CE pin should be high during all address transitions.

STR / OE

Input

50kΩ pull-up

Active-low common read/write strobe STR when BTYPE pin is low.

Active-low Output Enable OE when BTYPE pin is high.

Used for host read or write accesses to device RAM or registers.

WPOL

Input

50kΩ pull-up

Conguration pin for WAIT output polarity. When the WPOL pin is low, the “wait”

output is active low (WAIT). When WPOL is high, the “wait” output is active high

(WAIT).

WAIT / WAIT Output

Host bus read cycle WAIT or WAIT output. The HI-6130 WPOL input pin sets the

active level for this “wait” output.

Read cycles are slower than write cycles, but prefetching speeds data availability

for multi-word sequential address read cycles. For every new bus read cycle,

the HI-6130 asserts WAIT. Connected to the processor WAIT or WAIT input, this

action inserts one or more processor wait states (depending on processor clock

frequency) while the HI-6130 fetches the rst word. After reading each HI-6130

address. If the next bus access reads that sequential address, the data is ready

without WAIT assertion, even if that read cycle occurs some time later. While

the prefetch “chain” is broken by any write cycle, each read cycle prefetches

and retains data from the next address, whether or not it is needed. Thus WAIT

assertion only occurs for the rst word read.

The WAIT output is useful when the host processor runs at high clock rates and/

or when processor read wait states do not provide adequate timing margin for

worst case (slowest) read cycle timing for the HI-6130. Using the WAIT output

for the slow, rst read cycle means the processor bus interface can be optimized

to use faster no-wait cycles for write operations, and for reading words 2 through

N in successive address, N-word read operations. Processors lacking a WAIT

or WAIT input pin are typically congured to insert a xed number of wait states

for every read/write cycle.

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HOLTIC HI-613x系列：3.3V MIL-STD-1553B 多功能接口芯片

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