DP83848I：嵌入式以太网PHY芯片技术文档

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"DP83848i.pdf 是一款以太网网络接口芯片的详细技术文档，主要介绍了德州仪器（TI）的DP83848C/I/VYB/YB系列PHYTER™ QFP单端口10/100Mb/s以太网物理层传输器。这款芯片适用于嵌入式系统和STM32等微控制器的以太网网络接口，支持多种功能和标准，如IEEE 802.3、10BASE-T、100BASE-TX等。" 本文档详细阐述了DP83848I芯片的主要特性，它是一款高性能的以太网物理层收发器，适用于各种温度范围从-40°C到105°C的环境。该芯片采用低功耗的3.3V、0.18微米CMOS工艺技术，典型工作功率低于270毫瓦，这使得它非常适合于能源效率要求高的应用。 DP83848I支持多种网络标准，包括IEEE 802.3 ENDEC（编码解码器），10BASE-T和100BASE-TX的收发器及滤波器。此外，它还具备低功耗的特性，能有效减少系统的整体能耗。该芯片提供了3.3V的MAC接口，与微控制器的通信更加便捷。 DP83848I集成了自动MDIX功能，这意味着它可以自动识别并配置直通或交叉线缆，简化了网络连接的设置。它还支持ANSI X3.263兼容的TP-PMD，具有能量检测模式，以及物理子层的自适应均衡和基线漂移补偿，确保在长达150米的电缆上实现无错误操作。该芯片提供了一个25MHz的时钟输出，支持SNI（系统网络接口）和RMII（减少介质独立接口）两种可配置接口，适应不同的设计需求。同时，它还配备了MIISerial Management Interface (MDC和MDIO)，用于管理PHY的状态，并且支持IEEE 802.3 MII标准。DP83848I具有完整的PHY状态单寄存器访问功能，方便用户监控网络状态。此外，该芯片还提供了可编程LED支持，可以显示链接状态、速度（10/100Mb/s）、活动、双工模式和冲突检测。通过这些功能，用户可以在硬件层面直观地了解网络连接情况。最后，DP83848I支持IEEE 802.3的自动协商（Auto-Negotiation）功能，可以自动检测并匹配连接的网络设备的最佳工作模式，包括全双工和半双工、速度等参数，确保了网络连接的兼容性和灵活性。 DP83848I是一款全面的以太网网络接口解决方案，适用于嵌入式系统和STM32等微控制器，其丰富的功能和优化的性能使其成为各种工业和消费电子产品的理想选择。通过利用该芯片，开发者能够构建高效、可靠的以太网连接，满足现代网络设备的需求。

DP83848C

DP83848I

DP83848VYB, DP83848YB

SNLS266E –MAY 2007–REVISED MARCH 2015

www.ti.com

AC Timing Requirements (continued)

PARAMETER DESCRIPTION NOTES MIN TYP MAX UNIT

100BASE-TX TRANSMIT TIMING (t

R/F

and Jitter)

100 Mb/s PMD Output Pair t

3 4 5 ns

and t

(6)

T2.8.1

100 Mb/s t

and t

500 ps

Mismatch

(7)(6)

100 Mb/s PMD Output Pair

T2.8.2 1.4 ns

Transmit Jitter

100BASE-TX RECEIVE PACKET LATENCY TIMING

(8)

T2.9.1 Carrier Sense ON Delay

(9)

100 Mb/s Normal mode

(10)

20 bits

T2.9.2 Receive Data Latency 100 Mb/s Normal mode

(10)

24 bits

100BASE-TX RECEIVE PACKET DEASSERTION TIMING

T2.10.1 Carrier Sense OFF Delay

(11)

100 Mb/s Normal mode

(10)

24 bits

10 Mb/s MII TRANSMIT TIMING

(12)

T2.11.1 TX_CLK High/Low Time 10 Mb/s MII mode 190 200 210 ns

TXD[3:0], TX_EN Data Setup to

T2.11.2 10 Mb/s MII mode 25 ns

TX_CLK fall

TXD[3:0], TX_EN Data Hold

T2.11.3 10 Mb/s MII mode 0 ns

from TX_CLK rise

10 Mb/s MII RECEIVE TIMING

T2.12.1 RX_CLK High/Low Time

(13)

160 200 240 ns

RX_CLK TO RXD[3:0}, RX_DV

T2.12.2 10 Mb/s MII mode 100 ns

Delay

RX_CLK rising edge delay from

T2.12.3 10 Mb/s MII mode 100 ns

RXD[3:0], RX_DV Valid

10 Mb/s SERIAL MODE (SNI) TRANSMIT TIMING

T2.13.1 TX_CLK High Time 10 Mb/s Serial mode (SNI) 20 25 30 ns

T2.13.2 TX_CLK Low Time 10 Mb/s Serial mode (SNI) 70 75 80 ns

TXD_0, TX_EN Data Setup to

T2.13.3 10 Mb/s Serial mode (SNI) 25 ns

TX_CLK rise

TXD_0, TX_EN Data Hold from

T2.13.4 10 Mb/s Serial mode (SNI) 0 ns

TX_CLK rise

10 Mb/s SERIAL MODE (SNI) RECEIVE TIMING

T2.14.1 RX_CLK High/Low Time

(14)

35 50 65 ns

RX_CLK fall to RXD_0, RX_DV

T2.14.2 10 Mb/s Serial mode (SNI) –10 10 ns

Delay

10BASE-T TRANSMIT TIMING (START OF PACKET)

Transmit Output Delay from the

T2.15.1 10 Mb/s MII mode

(15)

3.5 bits

Falling Edge of TX_CLK

Transmit Output Delay from the

T2.15.2 10 Mb/s Serial mode (SNI)

(15)

3.5 bits

Rising Edge of TX_CLK

(6) Rise and fall times taken at 10% and 90% of the +1 or -1 amplitude

(7) Normal Mismatch is the difference between the maximum and minimum of all rise and fall times

(8) PMD Input Pair voltage amplitude is greater than the Signal Detect Turnon Threshold Value.

(9) Carrier Sense On Delay is determined by measuring the time from the first bit of the “J” code group to the assertion of Carrier Sense.

(10) 1 bit time = 10 ns in 100 Mb/s mode.

(11) Carrier Sense Off Delay is determined by measuring the time from the first bit of the “T” code group to the deassertion of Carrier Sense.

(12) An attached Mac should drive the transmit signals using the positive edge of TX_CLK. As shown above, the MII signals are sampled on

the falling edge of TX_CLK.

(13) RX_CLK may be held low for a longer period of time during transition between reference and recovered clocks. Minimum high and low

times will not be violated.

(14) RX_CLK may be held high for a longer period of time during transition between reference and recovered clocks. Minimum high and low

times will not be violated.

(15) 1 bit time = 100 ns in 10 Mb/s.

Submit Documentation Feedback

Product Folder Links: DP83848C DP83848I DP83848VYB DP83848YB

DP83848C

DP83848I

DP83848VYB, DP83848YB

www.ti.com

SNLS266E –MAY 2007–REVISED MARCH 2015

AC Timing Requirements (continued)

PARAMETER DESCRIPTION NOTES MIN TYP MAX UNIT

10BASE-T TRANSMIT TIMING (END OF PACKET)

End of Packet High Time

T2.16.1 250 300 ns

(with '0' ending bit)

End of Packet High Time

T2.16.2 250 300 ns

(with '1' ending bit)

10BASE-T RECEIVE TIMING (START OF PACKET)

(16)

Carrier Sense Turnon Delay

T2.17.1 630 1000 ns

(PMD Input Pair to CRS)

T2.17.2 RX_DV Latency

(17)

10 bits

T2.17.3 Receive Data Latency Measurement shown from SFD 8 bits

10BASE-T RECEIVE TIMING (END OF PACKET)

T2.18.1 Carrier Sense Turn Off Delay 1 µs

10 Mb/s HEARTBEAT TIMING

T2.19.1 CD Heartbeat Delay 10 Mb/s half-duplex mode 1200 ns

T2.19.2 CD Heartbeat Duration 10 Mb/s half-duplex mode 1000 ns

10 Mb/s JABBER TIMING

T2.20.1 Jabber Activation Time 85 ms

T2.20.2 Jabber Deactivation Time 500 ms

10BASE-T NORMAL LINK PULSE TIMING

(18)

T2.21.1 Pulse Width 100 ns

T2.21.2 Pulse Period 16 ms

AUTO-NEGOTIATION FAST LINK PULSE (FLP) TIMING

(18)

T2.22.1 Clock, Data Pulse Width 100 ns

Clock Pulse to Clock Pulse

T2.22.2 125 µs

Period

Clock Pulse to Data Pulse

T2.22.3 Data = 1 62 µs

Period

T2.22.4 Burst Width 2 ms

T2.22.5 FLP Burst to FLP Burst Period 16 ms

100BASE-TX SIGNAL DETECT TIMING

(19)

T2.23.1 SD Internal Turnon Time 1 ms

T2.23.2 SD Internal Turnoff Time 350 µs

100 Mb/s INTERNAL LOOPBACK TIMING

T2.24.1 TX_EN to RX_DV Loopback

(20)

100 Mb/s internal loopback mode

(21)

240 ns

10 Mb/s INTERNAL LOOPBACK TIMING

T2.25.1 TX_EN to RX_DV Loopback

(20)

10 Mb/s internal loopback mode 2 µs

RMII TRANSMIT TIMING

T2.26.1 X1 Clock Period 50 MHz Reference Clock 20 ns

TXD[1:0], TX_EN, Data Setup

T2.26.2 4 ns

to X1 rising

TXD[1:0], TX_EN, Data Hold

T2.26.3 2 ns

from X1 rising

(16) 1 bit time = 100 ns in 10 Mb/s mode.

(17) 10BASE-T RX_DV Latency is measured from first bit of preamble on the wire to the assertion of RX_DV

(18) These specifications represent transmit timings.

(19) The signal amplitude on PMD Input Pair must be TP-PMD compliant.

(20) Measurement is made from the first rising edge of TX_CLK after assertion of TX_EN.

(21) Due to the nature of the descrambler function, all 100BASE-TX Loopback modes will cause an initial “dead-time” of up to 550 µs during

which time no data will be present at the receive MII outputs. The 100BASE-TX timing specified is based on device delays after the

initial 550µs “dead-time”.

Submit Documentation Feedback

Product Folder Links: DP83848C DP83848I DP83848VYB DP83848YB

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