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首页RISC-V P-Extension提案:全貌与应用指南
RISC-V P-Extension提案:全貌与应用指南
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更新于2024-06-16
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RISC-V DSP扩展指令集提案(P-ext-proposal.pdf)是RISC-V架构的重要补充,它针对RISC-V处理器提供了针对数字信号处理(DSP)操作的增强功能。这份文档处于开发状态,版本0.9.11-draft-20211209,旨在帮助开发者理解和利用P扩展。 P扩展的核心内容包括SIMD(单指令流多数据流)数据处理指令的多个子集。首先,16位和8位的加法、减法、移位、比较、乘法以及一些其他通用指令被详细列出,覆盖了不同宽度的数据类型。这些指令允许高效处理大量并行计算任务,如音频、视频和机器学习应用。 文档特别关注部分SIMD处理指令,如16位打包指令、特定乘加运算(如"32x32"和"32x16"),以及16位乘法与32位加减的组合操作,这些设计旨在优化对性能敏感的应用中的算术密集型任务。 P扩展还包括新的用户控制和状态寄存器,它们用于管理和跟踪处理器的状态,这对于确保系统的稳定性和性能至关重要。此外,编码表提供了对新指令的详细编码规则,帮助硬件设计师和软件开发者正确实现和理解这些扩展。 值得注意的是,文档强调了在使用P扩展时可能存在的兼容性问题,因为某些指令可能会与现有的RVB(RISC-V Base)指令集有重叠,因此开发者需要谨慎处理,避免潜在冲突。同时,开发者也需要关注文档的更新状态,以防早期版本的指令集变化影响实际应用。 RISC-V DSP扩展指令集提案为RISC-V架构的高性能处理能力提供了重要的增强,对于那些寻求利用RISC-V进行高效 DSP 开发的工程师来说,理解和掌握这一扩展对于提升系统性能和优化工作负载具有关键价值。
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Chapter 1. Introduction
Digital Signal Processing (DSP), has emerged as an important technology for modern electronic
systems. A wide range of modern applications employ DSP algorithms to solve problems in their
particular domains, including sensor fusion, servo motor control, audio decode/encode, speech
synthesis and coding, MPEG4 decode, medical imaging, computer vision, embedded control,
robotics, human interface, etc.
The proposed P instruction set extension increases the DSP algorithm processing capabilities of the
RISC-V CPU IP products. With the addition of the RISC-V P instruction set extension, the RISC-V CPUs
can now run these various DSP applications with lower power and higher performance.
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Chapter 2. Shorthand Definitions and
Terminology
2.1. Shorthand Definitions
• r.H == rH1: r[31:16], r.L == r.H0: r[15:0]
• r.B3: r[31:24], r.B2: r[23:16], r.B1: r[15:8], r.B0: r[7:0]
• r.B[x]: r[(x*8+7):(x*8+0)]
• r.H[x]: r[(x*16+15):(x*16+0)]
• r.W[x]: r[(x*32+31):(x*32+0)]
• r.D[x]: r[(x*64+63):(x*64+0)]
• r[xU]: the upper 32-bit of a 64-bit number; xU represents the GPR number that contains this
upper part 32-bit value.
• r[xL]: the lower 32-bit of a 64-bit number; xL represents the GPR number that contains this
lower part 32-bit value.
• r[xU].r[xL]: a 64-bit number that is formed from a pair of GPRs.
• s>>: signed arithmetic right shift.
• u>>: unsigned logical right shift.
• u<<: logical left shift, shifting in 0 from the right side.
• SAT.Qn(): Saturate to the range of [-2
n
, 2
n
-1], if saturation happens, set OV flag.
• SAT.Um(): Saturate to the range of [0, 2
m
-1], if saturation happens, set OV flag.
• ROUND(): Indicate “rounding”, i.e., add 1 to the most significant discarded bit for right shift or
MSW-type multiplication instructions.
• SUM(): Summation of all data elements.
• Sign or Zero Extending functions:
◦ SEm(data): Sign-Extend data to m-bit.
◦ SE_XLEN(data): Sign-Extend data to XLEN-bit.
◦ ZEm(data): Zero-Extend data to m-bit.
◦ ZE_XLEN(data): Zero-Extend data to XLEN-bit.
• ABS(x): Calculate the absolute value of “x”.
• CONCAT(x,y): Concatinate “x” and “y” to form a value.
• u<: Unsigned less than comparison.
• u≤: Unsigned less than & equal comparison.
• u>: Unsigned greater than comparison.
• s<: Signed less than comparison.
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• s≤: Signed less than & equal comparison.
• s>: Signed greater than comparison.
• s*: Signed multiplication.
• u*: Unsigned multiplication.
• su*: Signed and Unsigned multiplication.
2.2. Terminology
• GPR: General purpose register.
• Q-format (Qm.n): It describes a signed binary fixed point number format. "m" is the number of
bits, including the sign bit and integer bits, before a notional binary point, and "n" is the
number of fraction bits that follow it. This notation represents a signed binary fixed point value
in the range of -2^(m-1) (inclusive) and 2^(m-1) (exclusive), with 2^(m+n) unique values
available in that range. For example, Q1.15 represents a number in the range of -1 (inclusive)
and 1 (exclusive), with 65536 unique values available in that range.
• Qn: A shorthand format for Q1.n. For example, Q7, Q15, Q31, Q63.
• Um: It represents an unsigned binary number in the range of 0 and (2^m)-1.
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Chapter 3. RISC-V P Extension Instruction
Summary
3.1. SIMD Data Processing Instructions
3.1.1. 16-bit Addition & Subtraction Instructions
Based on the combination of the types of the two 16-bit arithmetic operations within a 32-bit word
element, the SIMD 16-bit add/subtract instructions can be classified into 6 main categories: Addition
(two 16-bit addition), Subtraction (two 16-bit subtraction), Crossed Add & Sub (one addition and one
subtraction), and Crossed Sub & Add (one subtraction and one addition), Straight Add & Sub (one
addition and one subtraction), and Straight Sub & Add (one subtraction and one addition).
Based on the way of how an overflow condition is handled, the SIMD 16-bit add/subtract
instructions can be classified into 5 groups: Wrap-around (dropping overflow), Signed Halving
(keeping overflow by dropping 1 LSB bit), Unsigned Halving, Signed Saturation (clipping overflow),
and Unsigned Saturation.
Together, there are 30 SIMD 16-bit add/subtract instructions.
Table 1. SIMD 16-bit Add/Subtract Instructions
No. Mnemonic Instruction Operation
1 ADD16 rd, rs1, rs2 16-bit Addition
rd.H[x] = rs1.H[x] + rs2.H[x];
(RV32: x=1..0, RV64: x=3..0)
2 RADD16 rd, rs1, rs2
16-bit Signed
Halving Addition
a17[x] = SE17(rs1.H[x]);
b17[x] = SE17(rs2.H[x]);
t17[x] = a17[x] + b17[x];
rd.H[x] = t17[x] s>> 1;
(RV32: x=1..0, RV64: x=3..0)
3 URADD16 rd, rs1, rs2
16-bit Unsigned
Halving Addition
a17[x] = ZE17(rs1.H[x]);
b17[x] = ZE17(rs2.H[x]);
t17[x] = a17[x] + b17[x];
rd.H[x] = t17[x] u>> 1;
(RV32: x=1..0, RV64: x=3..0)
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