Section number Title Page
10.5 Functional description...................................................................................................................................................470
10.5.1 Transaction protocol..................................................................................................................................470
10.5.1.1 START condition...................................................................................................................471
10.5.1.2 Slave address transmission.....................................................................................................471
10.5.1.3 Repeated START condition...................................................................................................472
10.5.1.4 STOP condition......................................................................................................................473
10.5.1.5 Protocol implementation details.............................................................................................473
10.5.1.5.1 Transaction monitoring-implementation details.............................................473
10.5.1.5.2 Control transfer-implementation details.........................................................473
10.5.1.6 Address compare-implementation details..............................................................................474
10.5.2 Arbitration procedure.................................................................................................................................475
10.5.2.1 Arbitration control..................................................................................................................475
10.5.3 Handshaking...............................................................................................................................................476
10.5.4 Clock control..............................................................................................................................................476
10.5.4.1 Clock synchronization............................................................................................................476
10.5.4.2 Input synchronization and digital filter..................................................................................477
10.5.4.2.1 Input signal synchronization...........................................................................477
10.5.4.2.2 Filtering of SCL and SDA lines......................................................................477
10.5.4.3 Clock stretching.....................................................................................................................477
10.5.5 Boot sequencer mode.................................................................................................................................478
10.5.5.1 EEPROM calling address.......................................................................................................479
10.5.5.2 EEPROM data format............................................................................................................479
10.6 Initialization/application information...........................................................................................................................482
10.6.1 Initialization sequence................................................................................................................................482
10.6.2 Generation of START................................................................................................................................483
10.6.3 Post-transfer software response.................................................................................................................483
10.6.4 Generation of STOP...................................................................................................................................484
10.6.5 Generation of repeated START.................................................................................................................484
10.6.6 Generation of SCL when SDA low............................................................................................................484
P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013
18 Freescale Semiconductor, Inc.