英飞凌ICE3RBR1765JG 650V CoolSET™中文版规格书 2017-06-13 Revision 1.1

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ICE3RBR1765JG是一款英飞凌芯片，提供了中文版规格书手册。该芯片采用DS0-12封装，并具有以下产品亮点： 1. 采用主动爆发模式以达到低于50 mW的待机功率。 2. 提供超载、过温和过压的自动重启保护功能。 3. 外部自动重启使能功能。 4. 内建软起动和空白窗口功能。 5. 可扩展的空白窗口以适应高负载跳变。 6. 内建频率抖动和软驱动功能，以降低辐射电磁干扰。 7. 使用绿色模具胶料。 8. 无铅引线涂层，符合RoHS标准。 9. 650 V坚固的CoolMOS™技术，具备内建的启动电路。 10. 采用主动爆发模式以实现最低的待机功率。 11. 在主动爆发模式下能够快速响应负载跳变。 12. 内部 65 kHz 振荡器。该芯片规格书手册还提供了重要的注意事项和警告，修订版本为1.1，发布日期为2017年6月13日。

Data Sheet 6 Revision 1.1

2017-06-13

Fixed-Frequency, 650V CoolSET™ in DS0-12 Package

Functional Description

3.2 Power Management

Internal Bias

Voltage

Reference

Power Management

5.0V

Undervoltage Lockout

18V

10.5V

Power-Down Reset

Active Burst Mode

Auto Restart

Mode

Startup Cell

VCCDrain

Depl. CoolMOS™

Soft Start block

Figure 4 Power Management

The Undervoltage Lockout monitors the external supply voltage V

VCC

. When the SMPS is plugged to the main

line the internal Startup Cell is biased and starts to charge the external capacitor C

VCC

which is connected to the

VCC pin. This VCC charge current is controlled to 0.9 mA by the Startup Cell. When the V

VCC

exceeds the on-

threshold V

VCCon

=18 V the bias circuit are switched on. Then the Startup Cell is switched off by the Undervoltage

Lockout and therefore no power losses present due to the connection of the Startup Cell to the Drain voltage.

To avoid uncontrolled ringing at switch-on, a hysteresis start up voltage is implemented. The switch-off of the

controller can only take place when V

VCC

falls below 10.5 V after normal operation was entered. The maximum

current consumption before the controller is activated is about 150 mA.

When V

VCC

falls below the off-threshold V

VCCoff

=10.5 V, the bias circuit is switched off and the soft start counter is

reset. Thus it is ensured that at every startup cycle the soft start starts at zero.

The internal bias circuit is switched off if Auto Restart Mode is entered. The current consumption is then

reduced to 150mA.

Once the malfunction condition is removed, this block will then turn back on. The recovery from Auto Restart

Mode does not require re-cycling the AC line.

When Active Burst Mode is entered, the internal Bias is switched off most of the time but the Voltage Reference

is kept alive in order to reduce the current consumption below 450 µA.

Data Sheet 7 Revision 1.1

2017-06-13

Fixed-Frequency, 650V CoolSET™ in DS0-12 Package

Functional Description

3.3 Improved Current Mode

x3.3

PWM OP

Improved

Current Mode

0.67V

PWM-Latch

Driver

Soft-Start Comparator

Figure 5 Current Mode

Current Mode means the duty cycle is controlled by the slope of the primary current. This is done by comparing

the FB signal with the amplified current sense signal.

Amplified Current Signal

0.67V

Driver

Figure 6 Pulse Width Modulation

In case the amplified current sense signal exceeds the FB signal the on-time T

of the driver is finished by

resetting the PWM-Latch (Figure 6).

The primary current is sensed by the external series resistor R

Sense

inserted in the source of the integrated

CoolMOS

. By means of Current Mode regulation, the secondary output voltage is insensitive to the line

variations. The current waveform slope will change with the line variation, which controls the duty cycle.

The external RSense allows an individual adjustment of the maximum source current of the integrated

CoolMOS

To improve the Current Mode during light load conditions the amplified current ramp of the PWM-OP is

superimposed on a voltage ramp, which is built by the switch T2, the voltage source V1 and a resistor R1 (Figure

7). Every time the oscillator shuts down for maximum duty cycle limitation the switch T2 is closed by V

OSC

. When

the oscillator triggers the Gate Driver, T2 is opened so that the voltage ramp can start.

In case of light load the amplified current ramp is too small to ensure a stable regulation. In that case the

Voltage Ramp is a well defined signal for the comparison with the FB-signal. The duty cycle is then controlled

by the slope of the Voltage Ramp.

By means of the time delay circuit which is triggered by the inverted V

OSC

signal, the Gate Driver is switched-off

until it reaches approximately 156 ns delay time (Figure 8). It allows the duty cycle to be reduced continuously

till 0% by decreasing V

below that threshold.

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