TLC1543系列AD转换芯片详解：10位模拟-数字转换器
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TLC1543是一款由Texas Instruments公司生产的10位模拟信号到数字信号（AD）转换器，专为工业级应用设计。这款芯片具有显著的特点，包括：
1. **高分辨率**：TLC1543系列（如TLC1543C、TLC1543I和TLC1543Q）提供了10位的分辨率，这意味着它可以将输入的模拟信号精确地转换为数字信号，确保了极高的精度。
2. **多通道接口**：该芯片拥有11个模拟输入通道，可以同时处理多个传感器或信号源的数据，提高了系统集成度和效率。
3. **内置自测试功能**：设备内置三种不同的自测试模式，有助于检测和验证芯片性能，增强了可靠性。
4. **内置采样保持功能**：通过内置采样保持电路，能够稳定信号并在转换期间防止外部干扰，确保转换结果的一致性。
5. **低误差率**：总未校准误差控制在±1LSB（最大），这是衡量AD转换器准确性的关键指标。
6. **系统时钟**：TLC1543内置时钟，无需外部时钟源，减少了设计复杂性和成本。
7. **串行控制接口**：采用四线接口（包括片选线CS、输入/输出时钟I/OCLK、地址输入ADDRESS和数据输出DATAOUT），方便与主机处理器的串行端口直接通信，支持高速数据传输。
8. **多路复用器**：芯片内部集成了一个14通道多路复用器，允许用户灵活选择哪个通道进行转换，增加了灵活性。
9. **CMOS技术**：TLC1543系列采用CMOS工艺制造，这提供了低功耗、长寿命和优良的抗干扰性能。
10. **兼容性**：TLC1543的设计是与TLC1542系列兼容的，这意味着它可以在现有的系统中替换，降低了升级成本。
TLC1543是一款功能强大且易于集成的AD转换器，适用于需要高精度和高速数据处理的应用，广泛应用于工业自动化、仪表测量、信号处理等领域。
TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052C – MARCH 1992 – REVISED MARCH 1995
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
detailed description (continued)
There are six basic serial-interface timing modes that can be used with the device. These modes are determined
by the speed of I/O CLOCK and the operation of CS
as shown in Table 1. These modes are (1) a fast mode with
a 10-clock transfer and CS
inactive (high) between conversion cycles, (2) a fast mode with a 10-clock transfer
and CS
active (low) continuously, (3) a fast mode with an 11- to 16-clock transfer and CS inactive (high) between
conversion cycles, (4) a fast mode with a 16-bit transfer and CS
active (low) continuously, (5) a slow mode with
an 11- to 16-clock transfer and CS
inactive (high) between conversion cycles, and (6) a slow mode with a
16-clock transfer and CS
active (low) continuously.
The MSB of the previous conversion appears at DATA OUT on the falling edge of CS
in mode 1, mode 3, and
mode 5, on the rising edge of EOC in mode 2 and mode 4, and following the sixteenth clock falling edge in
mode 6. The remaining nine bits are shifted out on the next nine falling edges of I/O CLOCK. Ten bits of data
are transmitted to the host-serial interface through DATA OUT. The number of serial clock pulses used also
depends on the mode of operation, but a minimum of ten clock pulses is required for conversion to begin. On
the tenth clock falling edge, the EOC output goes low and returns to the high logic level when conversion is
complete and the result can be read by the host. Also, on the tenth clock falling edge, the internal logic takes
DATA OUT low to ensure that the remaining bit values are zero if the I/O CLOCK transfer is more than ten clocks
long.
Table 1 lists the operational modes with respect to the state of CS
, the number of I/O serial transfer clocks that
can be used, and the timing edge on which the MSB of the previous conversion appears at the output.
Table 1. Mode Operation
MODES
CS
NO. OF
I/O CLOCKS
MSB AT DATA OUT
†
TIMING
DIAGRAM
FMd
Mode 1 High between conversion cycles 10 CS falling edge Figure 9
Fast Modes
Mode 2 Low continuously 10 EOC rising edge Figure 10
F
as
t
M
o
d
es
Mode 3 High between conversion cycles 11 to 16
‡
CS falling edge Figure 11
Mode 4 Low continuously 16
‡
EOC rising edge Figure 12
Slow Modes
Mode 5 High between conversion cycles 11 to 16
‡
CS falling edge Figure 13
Sl
ow
M
o
d
es
Mode 6 Low continuously 16
‡
16th clock falling edge Figure 14
†
These edges also initiate serial-interface communication.
‡
No more than 16 clocks should be used.
fast modes
The device is in a fast mode when the serial I/O CLOCK data transfer is completed before the conversion is
completed. With a 10-clock serial transfer, the device can only run in a fast mode since a conversion does not
begin until the falling edge of the tenth I/O CLOCK.
mode 1: fast mode, CS inactive (high) between conversion cycles, 10-clock transfer
In this mode, CS is inactive (high) between serial I/O CLOCK transfers and each transfer is ten clocks long. The
falling edge of CS
begins the sequence by removing DATA OUT from the high-impedance state. The rising edge
of CS
ends the sequence by returning DATA OUT to the high-impedance state within the specified delay time.
Also, the rising edge of CS
disables the I/O CLOCK and ADDRESS terminals within a setup time plus two falling
edges of the internal system clock.
mode 2: fast mode, CS active (low) continuously, 10-clock transfer
In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer is ten clocks long. After
the initial conversion cycle, CS
is held active (low) for subsequent conversions; the rising edge of EOC then
begins each sequence by removing DATA OUT from the low logic level, allowing the MSB of the previous
conversion to appear immediately on this output.
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