华邦W25Q64SPI闪存解读：64M容量详解与常用功能注释

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W25Q64（带书签版）（有笔记）是一份华邦电子公司出品的64M比特（8M字节）SPI闪存记忆体的详细技术文档。该文档针对W25Q64这一具体型号进行了解析，特别强调了其特点和使用时的注意事项，以方便英语水平不高的用户快速理解和学习。 W25Q64是一个SPI接口的存储器，它内部结构精细，由128个区域组成，每个区域包含64k字节，进一步划分为16个扇区，每个扇区又有4k字节的划分。这使得它在存储和管理数据时具有较高的密度和灵活性。文档中详细列出了W25Q64的各个引脚功能，包括片选（CS）、写保护（WP）、保持（HOLD）、串行时钟（CLK）、串行数据输入（DI）和输出（DO）。其中，CS需在新的指令执行前下降沿有效，而WP允许在高电平时读写，在低电平时只读取。 W25Q64提供了三种工作模式：模式0（CPOL=0, CPHA=0）、模式3（CPOL=1, CPHA=1），支持不同数据传输速率，标准模式下最大速度可达80M，快速模式160M，高速模式则能达到320M。值得注意的是，闪存中的数据只能由1变为0，想要修改数据必须先进行擦除操作。文档还包含了W25Q64的通用描述、特性、引脚配置以及不同封装类型（如SOIC208-MIL, WSON8X6-MM, PDIP300-MIL）的详细说明，包括各引脚的用途和功能。例如， ChipSelect（/CS）用于选择特定存储区域，DI和DO分别负责数据的输入和输出，而IO0等其他引脚也提供了额外的I/O功能。这份带有注解的手册为用户提供了一个实用的参考工具，不仅介绍了硬件设计者所需的技术参数，还便于初学者理解和操作W25Q64这款高性能的SPI闪存记忆体。无论是进行硬件设计还是故障排查，这份资料都具有很高的实用价值。

W25Q64BV

Publication Release Date: July 08, 2010

- 11 - Revision E

10. FUNCTIONAL DESCRIPTION

10.1 SPI OPERATIONS

10.1.1 Standard SPI Instructions

The W25Q64BV is accessed through an SPI compatible bus consisting of four signals: Serial Clock

(CLK), Chip Select (/CS), Serial Data Input (DI) and Serial Data Output (DO). Standard SPI instructions

use the DI input pin to serially write instructions, addresses or data to the device on the rising edge of

CLK. The DO output pin is used to read data or status from the device on the falling edge CLK.

SPI bus operation Modes 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and

Mode 3 concerns the normal state of the CLK signal when the SPI bus master is in standby and data is

not being transferred to the Serial Flash. For Mode 0 the CLK signal is normally low on the falling and

rising edges of /CS. For Mode 3 the CLK signal is normally high on the falling and rising edges of /CS.

10.1.2 Dual SPI Instructions

The W25Q64BV supports Dual SPI operation when using the “Fast Read Dual Output and Dual I/O” (3B

and BB hex) instructions. These instructions allow data to be transferred to or from the device at two to

three times the rate of ordinary Serial Flash devices. The Dual Read instructions are ideal for quickly

downloading code to RAM upon power-up (code-shadowing) or for executing non-speed-critical code

directly from the SPI bus (XIP). When using Dual SPI instructions the DI and DO pins become

bidirectional I/O pins: IO0 and IO1.

10.1.3 Quad SPI Instructions

The W25Q64BV supports Quad SPI operation when using the “Fast Read Quad Output”, “Fast Read

Quad I/O” and “Octal Word Read Quad I/O” (6B, EB and E3 hex respectively). These instructions allow

data to be transferred to or from the device four to six times the rate of ordinary Serial Flash. The Quad

Read instructions offer a significant improvement in continuous and random access transfer rates

allowing fast code-shadowing to RAM or execution directly from the SPI bus (XIP). When using Quad SPI

instructions the DI and DO pins become bidirectional IO0 and IO1, and the /WP and /HOLD pins become

IO2 and IO3 respectively. Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status

10.1.4 Hold Function

The /HOLD signal allows the W25Q64BV operation to be paused while it is actively selected (when /CS is

low). The /HOLD function may be useful in cases where the SPI data and clock signals are shared with

other devices. For example, consider if the page buffer was only partially written when a priority interrupt

requires use of the SPI bus. In this case the /HOLD function can save the state of the instruction and the

data in the buffer so programming can resume where it left off once the bus is available again. The

/HOLD function is only available for standard SPI and Dual SPI operation, not during Quad SPI.

To initiate a /HOLD condition, the device must be selected with /CS low. A /HOLD condition will activate

on the falling edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the

/HOLD condition will activate after the next falling edge of CLK. The /HOLD condition will terminate on the

rising edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the /HOLD

condition will terminate after the next falling edge of CLK. During a /HOLD condition, the Serial Data

Output (DO) is high impedance, and Serial Data Input (DI) and Serial Clock (CLK) are ignored. The Chip

Select (/CS) signal should be kept active (low) for the full duration of the /HOLD operation to avoid

resetting the internal logic state of the device.

W25Q64BV

- 12 -

10.2 WRITE PROTECTION

Applications that use non-volatile memory must take into consideration the possibility of noise and other

adverse system conditions that may compromise data integrity. To address this concern the W25Q64BV

provides several means to protect data from inadvertent writes.

10.2.1 Write Protect Features

• Device resets when VCC is below threshold

• Time delay write disable after Power-up

• Write enable/disable instructions and automatic write disable after program and erase

• Software and Hardware (/WP pin) write protection using Status Register

• Write Protection using Power-down instruction

• Lock Down write protection until next power-up

(1)

• One Time Program (OTP) write protection

(1)

Note 1: These features are available upon special order. Please contact Winbond for details.

Upon power-up or at power-down, the W25Q64BV will maintain a reset condition while VCC is below the

threshold value of V

WI, (See Power-up Timing and Voltage Levels and Figure 31). While reset, all

operations are disabled and no instructions are recognized. During power-up and after the VCC voltage

exceeds V

WI, all program and erase related instructions are further disabled for a time delay of tPUW. This

includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase and the Write Status

the VCC-min level and t

VSL time delay is reached. If needed a pull-up resister on /CS can be used to

accomplish this.

After power-up the device is automatically placed in a write-disabled state with the Status Register Write

Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page Program, Sector

Erase, Chip Erase or Write Status Register instruction will be accepted. After completing a program,

erase or write instruction the Write Enable Latch (WEL) is automatically cleared to a write-disabled state

of 0.

Software controlled write protection is facilitated using the Write Status Register instruction and setting

the Status Register Protect (SRP0, SRP1) and Block Protect (SEC,TB, BP2, BP1 and BP0) bits. These

settings allow a portion or all of the memory to be configured as read only. Used in conjunction with the

Write Protect (/WP) pin, changes to the Status Register can be enabled or disabled under hardware

control. See Status Register for further information. Additionally, the Power-down instruction offers an

extra level of write protection as all instructions are ignored except for the Release Power-down

instruction.

W25Q64BV

Publication Release Date: July 08, 2010

- 13 - Revision E

11. CONTROL AND STATUS REGISTERS

The Read Status Register-1 and Status Register-2 instructions can be used to provide status on the

availability of the Flash memory array, if the device is write enabled or disabled, the state of write

protection and the Quad SPI setting. The Write Status Register instruction can be used to configure the

devices write protection features and Quad SPI setting. Write access to the Status Register is controlled by

the state of the non-volatile Status Register Protect bits (SRP0, SRP1), the Write Enable instruction, and

in some cases the /WP pin.

11.1 STATUS REGISTER

11.1.1 BUSY

BUSY is a read only bit in the status register (S0) that is set to a 1 state when the device is executing a

Page Program, Sector Erase, Block Erase, Chip Erase or Write Status Register instruction. During this

time the device will ignore further instructions except for the Read Status Register and Erase Suspend

instruction (see t

W, tPP, tSE, tBE, and tCE in AC Characteristics). When the program, erase or write status

for further instructions.

11.1.2 Write Enable Latch (WEL)

Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to a 1 after executing a

Write Enable Instruction. The WEL status bit is cleared to a 0 when the device is write disabled. A write

disable state occurs upon power-up or after any of the following instructions: Write Disable, Page

Program, Sector Erase, Block Erase, Chip Erase and Write Status Register.

11.1.3 Block Protect Bits (BP2, BP1, BP0)

The Block Protect Bits (BP2, BP1, BP0) are non-volatile read/write bits in the status register (S4, S3, and

S2) that provide Write Protection control and status. Block Protect bits can be set using the Write Status

W in AC characteristics). All, none or a portion of the memory array can be

protected from Program and Erase instructions (see Status Register Memory Protection table). The

factory default setting for the Block Protection Bits is 0, none of the array protected.

11.1.4 Top/Bottom Block Protect (TB)

The non-volatile Top/Bottom bit (TB) controls if the Block Protect Bits (BP2, BP1, BP0) protect from the

Top (TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table.

The factory default setting is TB=0. The TB bit can be set with the Write Status Register Instruction

depending on the state of the SRP0, SRP1 and WEL bits.

11.1.5 Sector/Block Protect (SEC)

The non-volatile Sector protect bit (SEC) controls if the Block Protect Bits (BP2, BP1, BP0) protect 4KB

Sectors (SEC=1) or 64KB Blocks (SEC=0) in the Top (TB=0) or the Bottom (TB=1) of the array as shown

in the Status Register Memory Protection table. The default setting is SEC=0.

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