BCM5389 Linux驱动参照手册，便于移植b53驱动

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The BCM5389 is a single-chip 8-port SerDes Gigabit switch designed for connecting to external gigabit PHYs or fiber modules. It features eight 1.25 Gbps SerDes/SGMII port interfaces and provides a low-cost solution for Gigabit Ethernet-to-the-desktop applications. The BCM5389 Linux drivers in the net/dsa/b53 directory serve as a reference manual for porting the b53 driver, making it easier to integrate the switch into Linux-based systems. The preliminary datasheet for the BCM5389, dated 2/28/2007, provides detailed information on the switch's functionality and features. Located in Irvine, California, the datasheet is available from Broadcom Corporation. With its advanced capabilities and cost-effective design, the BCM5389 is a versatile solution for high-speed networking applications. Overall, the BCM5389 is a highly integrated and versatile gigabit switch suitable for a wide range of networking applications. Its eight port interfaces and SerDes/SGMII support make it an ideal choice for desktop Gigabit Ethernet connectivity. By using the Linux drivers provided in the net/dsa/b53 directory, developers can easily port the necessary drivers for the BCM5389, streamlining the integration process. The preliminary datasheet offers a comprehensive overview of the switch's features and functionality, making it a valuable resource for those looking to incorporate the BCM5389 into their networking setups. With its cost-effective design and advanced capabilities, the BCM5389 stands out as a top-tier solution for high-speed networking requirements.

2/28/2007 Y4XMF

BCM5389 Preliminary Data Sheet

2/28/07

Broadcom Corporation

Page xvi Document 5389-DS06-R

Table 104: Auto-Negotiation Expansion Register (Page 010h-017h: Address 0Ch-0Dh)112

Table 105: Extended Status Register (Page 010h-017h: Address 01Eh-01Fh)112

Table 106: SerDes/SGMII Control 1 Register (Page 010h-017h: Address 020h-021h)113

Table 107: Analog Transmit Register (Page 010h-017h: Address 020h-021h, Block 1)114

Table 108: SerDes/SGMII Control 2 Register (Page 010h-017h: Address 022h-023h)115

Table 109: SerDes/SGMII Control 3 Register (Page 010h-017h: Address 024h-025h)116

Table 110: SerDes/SGMII Status 1 Register (Page 010h-017h: Address 028h-029h)117

Table 111: SerDes/SGMII Status 2 Register (Page 010h-017h: Address 02Ah-02Bh)118

Table 112: SerDes/SGMII Status 3 Register (Page 010h-017h: Address 02Ch–02Dh)119

Table 113: BER/CRC Error Counter Register (Page 010h–017h: Address 02Eh-02Fh)119

Table 114: PRBS Control Register (Page 010h–017h: Address 030h-031h)120

Table 115: PRBS Status Register (Page 010h–017h: Address 032h-033h)120

Table 116: Pattern Generator Control Register (Page 010h–017h: Address 034h-035h)121

Table 117: Pattern Generator Status Register (Page 010h–017h: Address 036h-037h)122

Table 118: Force Transmit 1 Register (Page 010h–017h: Address 03Ah-30Bh)122

Table 119: Force Transmit 2 Register (Page 010h–017h: Address 03Ch-03Dh)122

Table 120: Block Address Number (Page 010h-017h: Address 03Eh-03Fh)123

Table 121: Port MIB Registers Page Summary123

Table 122: Page 020h–027h Port MIB Registers123

Table 123: Page 030h QoS Registers127

Table 124: QoS Global Control Register (Page 030h: Address 00h)128

Table 125: QoS IEEE 802.1P Enable Register (Page 030h: Address 04h–05h)128

Table 126: QoS DiffServ Enable Register (Page 030h: Address 06h–07h)129

Table 127: IEEE 802.1p Priority Map Register (Page 030h: Address 010h–013h)129

Table 128: DiffServ Priority Map 0 Register (Page 030h: Address 030h–035h)130

Table 129: DiffServ Priority Map 1 Register (Page 030h: Address 036h–03Bh)130

Table 130: DiffServ Priority Map 2 Register (Page 030h: Address 03Ch–041h)131

Table 131: DiffServ Priority Map 3 Register (Page 030h: Address 042h–407h)132

Table 132: Ingress Port Priority ID Map Register Address Summary132

Table 133: Ingress Port Priority ID Map Register (Page 030h: Address 050h–061h)133

Table 134: TX Queue Control Register (Page 030h: Address 080h)133

Table 135: TX Queue Weight Register Queue[0:3] (Page 030h: Address 081h–084h)134

Table 136: Page 031h VLAN Registers134

Table 137: Port-Based VLAN Control Register Address Summary134

Table 138: Port VLAN Control Register (Page 031h, Address 00h–0Fh)135

2/28/2007 Y4XMF

Preliminary Data Sheet BCM5389

2/28/07

Broadcom Corporation

Document 5389-DS06-R Page xvii

Table 139: Page 032h Trunking Registers135

Table 140: MAC Trunk Control Register (Page 032h, Address 01h)135

Table 141: Trunk Group Register (Page 032h, Address 090h–091h)136

Table 142: Page 034h IEEE 802.1Q VLAN Registers136

Table 143: Global IEEE 802.1Q Register (Pages 034h, Address 00h)137

Table 144: Global VLAN Control 1 Register (Page 034h, Address 01h)137

Table 145: Global VLAN Control 2 Register (Page 034h, Address 02h)138

Table 146: Global VLAN Control 3 Register (Page: 34h, Address 03h)139

Table 147: Global VLAN Control 4 Register (Page 034h, Address 04h)139

Table 148: Global VLAN Control 5 Register (Page 034h, Address 05h)140

Table 149: IEEE 802.1p Priority Remap Register (Page 034h, Address 07h-0Ah)141

Table 150: Default IEEE 802.1Q Tag Register Address Summary142

Table 151: Default IEEE 802.1Q Tag Register (Page 034h, Address 010h–021h)142

Table 152: Page 040h Jumbo Frame Control Register143

Table 153: Jumbo Frame Port Mask Registers (Page 040h, Address 01h-04h)143

Table 154: Jumbo MIB Good Frame Max Size Registers (Page 040h, Address 05h-06h)144

Table 155: Broadcast Storm Suppression Register (Page 041h)145

Table 156: Global Rate Control Register (Page 041h, Address 00h–03h)145

Table 157: Port Rate Control Register Address Summary147

Table 158: Port Rate Control Register (Page 041h, Address 010h–02Fh)147

Table 159: External PHY Registers (Serial Ports) Page Summary148

Table 160: External PHY Registers (Serial Ports) (Page 080h–087h)149

Table 161: Global Registers (Maps to All Pages)150

Table 162: SPI Data I/O Register (Maps to All Registers, Address 0F0h–0F7h)150

Table 163: SPI Status Register (Maps to All Registers, Address 0FEh)150

Table 164: Page Register (Maps to All Registers, Address 0FFh)150

Table 165: Absolute Maximum Ratings151

Table 166: Recommended Operating Conditions151

Table 167: Electrical Characteristics152

Table 168: Reset and Clock Timing153

Table 169: Serial Interface Output Timings154

Table 170: RvMII Mode Output Timings155

Table 171: RvMII Mode Input Timings156

Table 172: RGMII Output Timing (Normal Mode)157

Table 173: RGMII Output Timing (Delayed Mode)158

2/28/2007 Y4XMF

Preliminary Data Sheet BCM5389

2/28/07

Broadcom Corporation

Document 5389-DS06-R Introduction Page 1

Section 1: Introduction

OVERVIEW

The BCM5389 is a single-chip, 8-port switch device. The device provides:

• 9-port non-blocking 10/100/1000 Mbps switch controller

• Eight ports with SerDes/SGMII interface for connection to external 10/100/1000-Mbps Ethernet transceiver or SerDes

interface connection to 1000 Mbps full-duplex fiber module

• Eight integrated gigabit MACs (GMACs)

• One GMII/RGMII/RvMII port for PHY-less connection to the management agent

• An integrated Motorola SPI-compatible interface

• High-performance integrated packet buffer memory

• An address-resolution engine

The GMACs support full-duplex and half-duplex modes for 10 Mbps and 100 Mbps and full-duplex for 1000 Mbps. Flow

control is supported in the half-duplex mode with backpressure. In full-duplex mode, IEEE 802.3x frame-based flow control

is supported. The GMACs are IEEE 802.3-compliant and support maximum frame sizes of 9.6 KB.

An integrated address-management engine provides address learning and recognition functions at maximum frame rates.

The address table provides capacity for learning up to 4K unicast addresses. Addresses are added to the table after

receiving an error-free packet.

AUDIENCE

This document is for designers interested in integrating the BCM5389 switch into their hardware designs and for others who

need specific data about the physical characteristics and operation of the BCM5389 switch.

DATA SHEET INFORMATION

The following notational conventions are used in this document:

• Signal names are shown in uppercase letters (such as DATA).

• A bar over a signal name indicates that it is active low (such as CE

• In register and signal descriptions, [n:m] indicates a range from bit n to bit m (such as [7:0] indicates bits 7 through 0,

inclusive).

• The use of R or Reserved indicates that a bit or a field is reserved by Broadcom for future use. Typically, R is used for

individual bits and Reserved is used for fields.

• Numerical modifiers such as K or M follow traditional usage (for example, 1 KB means 1,024 bytes, 100 Mbps [referring

to fast Ethernet speed] means 100,000,000 bps, and 133 MHz means 133,000,000 Hz).

Note: The RvMII/GMII/RGMII port is used as a IMP (Management) Port only. It is not available for a PHY or

network port connection.

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