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PCI Express技术全面指南:1.x, 2.x, 3.0
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"PCIExpress TechnologyMikeJackson,RaviBudruk MindShare,Inc. MindShare TechnologySeries For training, visit mindshare.com"
PCI Express(PCIe)是一种高速接口标准,用于连接计算机系统中的外部设备,如显卡、网卡、硬盘等。PCIe技术由PCI Special Interest Group(PCI-SIG)开发并维护,旨在提供比传统PCI接口更快的数据传输速率和更低的延迟。PCIe采用串行数据传输方式,与传统的并行PCI总线相比,它能够更高效地利用带宽,并支持更高的数据传输速度。
Mike Jackson和Ravi Budruk合著的《PCI Express Technology》一书全面介绍了PCIe的1.x、2.x和3.0世代。这本书是理解PCIe复杂技术主题的重要资源,涵盖了从基本架构到高级特性的详细内容。书中可能包括以下知识点:
1. **PCIe架构**:PCIe的分层结构,包括物理层(PHY)、数据链接层(DLL)和事务层(TL),以及它们各自的功能。
2. **链路(Link)和Lane**:PCIe设备之间的通信是通过链接进行的,链接由一个或多个Lane组成。每个Lane可以双向传输数据,提供更高的带宽。
3. **电压和信号规范**:书中可能详细解释了PCIe的信号电平、眼图分析以及如何确保信号完整性的方法。
4. **速度和带宽**:不同世代的PCIe标准提供了不同的传输速度,例如PCIe 1.x为2.5GT/s,PCIe 2.x为5GT/s,PCIe 3.0为8GT/s,每个 Lane分别对应250MB/s、500MB/s和1GB/s的原始带宽(未考虑编码开销)。
5. **错误检测和纠正**:PCIe使用CRC(循环冗余校验)和其他机制来检测和纠正传输错误,确保数据的正确性。
6. **配置和状态空间**:PCIe设备的配置和管理,包括配置空间的访问、中断处理和热插拔支持。
7. **服务质量(QoS)**:PCIe如何通过流量控制、优先级和预留带宽来实现不同类型的流量的优先级处理。
8. **虚拟化支持**:现代系统中的PCIe设备虚拟化技术,如SR-IOV(单根I/O虚拟化)和VF(虚拟功能)。
9. **测试和调试**:书中可能包含关于如何使用工具和协议分析器来诊断和解决问题的信息。
10. **硬件设计和兼容性**:设计PCIe设备时要考虑的电气和机械规范,以及如何确保与其他设备的兼容性。
MindShare公司提供的不仅仅是书籍,他们还提供现场培训和自适应培训课程,帮助公司的技术人员更有效地学习和掌握这些复杂的技术。他们的课程由经验丰富的专家教授,这些专家具有深厚的行业知识和热情,能够帮助学员快速理解和应用所学知识,从而提高工作效率并降低培训成本。
Contents
xi
Unused Base and Limit Registers.................................................................................. 144
Sanity Check: Registers Used For Address Routing ....................................................... 144
TLP Routing Basics................................................................................................................ 145
Receivers Check For Three Types of Traffic ................................................................ 147
Routing Elements............................................................................................................. 147
Three Methods of TLP Routing...................................................................................... 147
General ....................................................................................................................... 147
Purpose of Implicit Routing and Messages .......................................................... 148
Why Messages?.................................................................................................. 148
How Implicit Routing Helps............................................................................ 148
Split Transaction Protocol............................................................................................... 149
Posted versus Non-Posted.............................................................................................. 150
Header Fields Define Packet Format and Type........................................................... 151
General ....................................................................................................................... 151
Header Format/Type Field Encodings ................................................................. 153
TLP Header Overview .................................................................................................... 154
Applying Routing Mechanisms .......................................................................................... 155
ID Routing......................................................................................................................... 155
Bus Number, Device Number, Function Number Limits................................... 155
Key TLP Header Fields in ID Routing................................................................... 155
Endpoints: One Check.............................................................................................. 156
Switches (Bridges): Two Checks Per Port ............................................................. 157
Address Routing .............................................................................................................. 158
Key TLP Header Fields in Address Routing ........................................................ 159
TLPs with 32-Bit Address................................................................................. 159
TLPs with 64-Bit Address................................................................................. 159
Endpoint Address Checking................................................................................... 160
Switch Routing.......................................................................................................... 161
Downstream Traveling TLPs (Received on Primary Interface).................. 162
Upstream Traveling TLPs (Received on Secondary Interface) ................... 163
Multicast Capabilities............................................................................................... 163
Implicit Routing ............................................................................................................... 163
Only for Messages .................................................................................................... 163
Key TLP Header Fields in Implicit Routing ......................................................... 164
Message Type Field Summary................................................................................ 164
Endpoint Handling................................................................................................... 165
Switch Handling ....................................................................................................... 165
DLLPs and Ordered Sets Are Not Routed......................................................................... 166
PCIe 3.0.book Page xi Sunday, September 2, 2012 11:25 AM
Contents
xii
Part Two: Transaction Layer
Chapter 5: TLP Elements
Introduction to Packet-Based Protocol............................................................................... 169
General............................................................................................................................... 169
Motivation for a Packet-Based Protocol ....................................................................... 171
1. Packet Formats Are Well Defined ...................................................................... 171
2. Framing Symbols Define Packet Boundaries.................................................... 171
3. CRC Protects Entire Packet ................................................................................. 172
Transaction Layer Packet (TLP) Details............................................................................. 172
TLP Assembly And Disassembly .................................................................................. 172
TLP Structure.................................................................................................................... 174
Generic TLP Header Format .......................................................................................... 175
General ....................................................................................................................... 175
Generic Header Field Summary............................................................................. 175
Generic Header Field Details ......................................................................................... 178
Header Type/Format Field Encodings ................................................................. 179
Digest / ECRC Field................................................................................................. 180
ECRC Generation and Checking..................................................................... 180
Who Checks ECRC? .......................................................................................... 180
Using Byte Enables ................................................................................................... 181
General ................................................................................................................ 181
Byte Enable Rules .............................................................................................. 181
Byte Enable Example......................................................................................... 182
Transaction Descriptor Fields ................................................................................. 182
Transaction ID.................................................................................................... 183
Traffic Class ........................................................................................................ 183
Transaction Attributes ...................................................................................... 183
Additional Rules For TLPs With Data Payloads.................................................. 183
Specific TLP Formats: Request & Completion TLPs................................................... 184
IO Requests................................................................................................................ 184
IO Request Header Format .............................................................................. 185
IO Request Header Fields................................................................................. 186
Memory Requests ..................................................................................................... 188
Memory Request Header Fields...................................................................... 188
Memory Request Notes .................................................................................... 192
Configuration Requests ........................................................................................... 192
Definitions Of Configuration Request Header Fields.................................. 193
Configuration Request Notes .......................................................................... 196
PCIe 3.0.book Page xii Sunday, September 2, 2012 11:25 AM
Contents
xiii
Completions............................................................................................................... 196
Definitions Of Completion Header Fields ..................................................... 197
Summary of Completion Status Codes .......................................................... 200
Calculating The Lower Address Field............................................................ 200
Using The Byte Count Modified Bit................................................................ 201
Data Returned For Read Requests: ................................................................. 201
Receiver Completion Handling Rules: ........................................................... 202
Message Requests ..................................................................................................... 203
Message Request Header Fields...................................................................... 204
Message Notes: .................................................................................................. 206
INTx Interrupt Messages.................................................................................. 206
Power Management Messages ........................................................................ 208
Error Messages................................................................................................... 209
Locked Transaction Support............................................................................ 209
Set Slot Power Limit Message.......................................................................... 210
Vendor-Defined Message 0 and 1 ................................................................... 210
Ignored Messages .............................................................................................. 211
Latency Tolerance Reporting Message........................................................... 212
Optimized Buffer Flush and Fill Messages.................................................... 213
Chapter 6: Flow Control
Flow Control Concept ........................................................................................................... 215
Flow Control Buffers and Credits....................................................................................... 217
VC Flow Control Buffer Organization.......................................................................... 218
Flow Control Credits ....................................................................................................... 219
Initial Flow Control Advertisement ................................................................................... 219
Minimum and Maximum Flow Control Advertisement ........................................... 219
Infinite Credits.................................................................................................................. 221
Special Use for Infinite Credit Advertisements........................................................... 221
Flow Control Initialization................................................................................................... 222
General............................................................................................................................... 222
The FC Initialization Sequence....................................................................................... 223
FC_Init1 Details................................................................................................................224
FC_Init2 Details................................................................................................................225
Rate of FC_INIT1 and FC_INIT2 Transmission .......................................................... 226
Violations of the Flow Control Initialization Protocol ............................................... 227
Introduction to the Flow Control Mechanism.................................................................. 227
General............................................................................................................................... 227
The Flow Control Elements............................................................................................ 227
Transmitter Elements ............................................................................................... 228
Receiver Elements..................................................................................................... 229
PCIe 3.0.book Page xiii Sunday, September 2, 2012 11:25 AM
Contents
xiv
Flow Control Example........................................................................................................... 230
Stage 1 — Flow Control Following Initialization........................................................ 230
Stage 2 — Flow Control Buffer Fills Up........................................................................ 233
Stage 3 — Counters Roll Over........................................................................................ 234
Stage 4 — FC Buffer Overflow Error Check ................................................................ 235
Flow Control Updates ........................................................................................................... 237
FC_Update DLLP Format and Content........................................................................ 238
Flow Control Update Frequency ................................................................................... 239
Immediate Notification of Credits Allocated ....................................................... 239
Maximum Latency Between Update Flow Control DLLPs................................ 240
Calculating Update Frequency Based on Payload Size and Link Width ......... 240
Error Detection Timer — A Pseudo Requirement ...................................................... 243
Chapter 7: Quality of Service
Motivation ............................................................................................................................... 245
Basic Elements ........................................................................................................................ 246
Traffic Class (TC)..............................................................................................................247
Virtual Channels (VCs) ................................................................................................... 247
Assigning TCs to each VC — TC/VC Mapping .................................................. 248
Determining the Number of VCs to be Used ....................................................... 249
Assigning VC Numbers (IDs) ................................................................................. 251
VC Arbitration ........................................................................................................................ 252
General............................................................................................................................... 252
Strict Priority VC Arbitration......................................................................................... 253
Group Arbitration............................................................................................................ 255
Hardware Fixed Arbitration Scheme..................................................................... 257
Weighted Round Robin Arbitration Scheme........................................................ 257
Setting up the Virtual Channel Arbitration Table ............................................... 258
Port Arbitration ...................................................................................................................... 261
General............................................................................................................................... 261
Port Arbitration Mechanisms......................................................................................... 264
Hardware-Fixed Arbitration................................................................................... 265
Weighted Round Robin Arbitration ...................................................................... 265
Time-Based, Weighted Round Robin Arbitration (TBWRR).............................. 266
Loading the Port Arbitration Tables ............................................................................. 267
Switch Arbitration Example........................................................................................... 269
Arbitration in Multi-Function Endpoints ......................................................................... 270
Isochronous Support .............................................................................................................272
Timing is Everything....................................................................................................... 273
How Timing is Defined............................................................................................ 274
How Timing is Enforced.......................................................................................... 275
PCIe 3.0.book Page xiv Sunday, September 2, 2012 11:25 AM
Contents
xv
Software Support ............................................................................................................. 275
Device Drivers........................................................................................................... 276
Isochronous Broker................................................................................................... 276
Bringing it all together .................................................................................................... 276
Endpoints................................................................................................................... 276
Switches...................................................................................................................... 278
Arbitration Issues .............................................................................................. 278
Timing Issues ..................................................................................................... 278
Bandwidth Allocation Problems ..................................................................... 280
Latency Issues .................................................................................................... 281
Root Complex............................................................................................................ 281
Problem: Snooping ............................................................................................ 281
Snooping Solutions............................................................................................ 282
Power Management.................................................................................................. 282
Error Handling.......................................................................................................... 282
Chapter 8: Transaction Ordering
Introduction............................................................................................................................. 285
Definitions............................................................................................................................... 286
Simplified Ordering Rules................................................................................................... 287
Ordering Rules and Traffic Classes (TCs) .................................................................... 287
Ordering Rules Based On Packet Type......................................................................... 288
The Simplified Ordering Rules Table ........................................................................... 288
Producer/Consumer Model .................................................................................................. 290
Producer/Consumer Sequence — No Errors .............................................................. 291
Producer/Consumer Sequence — Errors..................................................................... 295
Relaxed Ordering ................................................................................................................... 296
RO Effects on Memory Writes and Messages.............................................................. 297
RO Effects on Memory Read Transactions................................................................... 298
Weak Ordering ....................................................................................................................... 299
Transaction Ordering and Flow Control...................................................................... 299
Transaction Stalls ............................................................................................................. 300
VC Buffers Offer an Advantage..................................................................................... 301
ID Based Ordering (IDO) ..................................................................................................... 301
The Solution...................................................................................................................... 301
When to use IDO.............................................................................................................. 302
Software Control .............................................................................................................. 303
Deadlock Avoidance..............................................................................................................303
PCIe 3.0.book Page xv Sunday, September 2, 2012 11:25 AM
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