"TL28L92 UART收发器数据手册：3.3V/5V双通用异步收发器。"

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The TI-TL28L92.pdf is a data manual for the TL28L92, a 3.3-V/5-V Dual Universal Asynchronous Receiver/Transmitter (UART) produced by Texas Instruments. The document provides detailed information on the product, including its specifications, features, and applications. The TL28L92 is a versatile UART transceiver that can operate at both 3.3-V and 5-V voltage levels, making it suitable for a wide range of industrial and consumer electronics applications. The data manual covers various aspects of the TL28L92, including its general description, electrical characteristics, functional block diagram, pin configurations, and recommended operating conditions. It also includes information on the device's features, such as its dual UART channels, programmable baud rate generator, FIFO buffers, and support for multiple data formats. The document provides guidance on how to interface the TL28L92 with other electronic components, as well as programming instructions for configuring its settings. It is important to note that the information provided in the data manual is based on the production data available at the time of publication. Texas Instruments adheres to strict quality standards to ensure that its products meet specifications and performance requirements. However, production processing may not always include testing of all parameters, so users are advised to refer to the most current documentation and consult with TI's technical support team for any specific inquiries. In conclusion, the TL28L92 is a reliable and versatile UART transceiver designed for industrial and consumer electronics applications. The data manual serves as a comprehensive guide for understanding the device's features, specifications, and performance characteristics. With Texas Instruments' commitment to quality and customer support, users can trust in the TL28L92 for their UART communication needs.

TL28L92FR

(80xxxmode)

CEN

RESET

RD X1/CLK

RxD

RxDA

TxD

TxDA

OP0

OP2

OP4

OP6

N.C.

IP1

IP3

INTR

IP4

IP5

IP6

IP2

TL28L92FR

(68xxxmode)

CEN

RESETN

R/W

DACK X1/CLK

RxD

RxDA

TxD

TxDA

OP OP0

OP OP2

OP OP4

OP OP6

N.C.

IP1

IP3

INTR

IP4

IP5

IACKN

IP2

TL28L92

www.ti.com

SLLS890B–AUGUST 2008–REVISED AUGUST 2009

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TL28L92

www.ti.com

SLLS890B–AUGUST 2008–REVISED AUGUST 2009

Table 1-1. PIN DESCRIPTION FOR 80xxx INTERFACE

TERMINAL

TYPE DESCRIPTION

QFP (FR) QFN (RGZ)

NAME

PIN NO. PIN NO.

I/M 11 7 I Bus configuration: When HIGH or not connected configures the bus interface to the

conditions shown in this table.

D0, D1, 22, 12, 23, 14, I/O Data bus: Bidirectional 3-state data bus used to transfer commands, data and status

D2, D3, 21,13, 22,15, between the DUART and the CPU. D0 is the least significant bit.

D4, D5, 20, 14, 21, 16,

D6, D7 19, 15 20, 17

CEN 33 35 I Chip enable: active LOW input signal. When LOW, data transfers between the CPU

and the DUART are enabled on D0 to D7 as controlled by the WRN, RDN and A0 to

A3 inputs. When HIGH, places the D0 to D7 lines in the 3-state condition.

WRN 3 3 I Write strobe: When LOW and CEN is also LOW, the contents of the data bus is

loaded into the addressed register. The transfer occurs on the rising edge of the

signal.

RDN 4 4 I Read strobe: When LOW and CEN is also LOW, causes the contents of the

addressed register to be presented on the data bus. The read cycle begins on the

falling edge of RDN.

A0, A1, 40, 42, 44, 46, I Address inputs: Select the DUART internal registers and ports for read/write

A2, A3 44, 1 48, 1 operations.

RESET 32 34 I Reset: A HIGH level clears internal registers (SRA, SRB, IMR, ISR, OPR and

OPCR), puts OP0 to OP7 in the HIGH state, stops the counter/timer, and puts

channels A and B in the inactive state, with the TxDA and TxDB outputs in the mark

(HIGH) state. Sets MR pointer to MR1. See Figure 5-2.

INTRN 18 19 O Interrupt request: Active LOW, open-drain, output which signals the CPU that one or

more of the eight maskable interrupting conditions are true. This pin requires a

pull-up device.

X1/CLK 30 32 I Crystal 1: Crystal or external clock input. A crystal or clock of the specified limits

must be supplied at all times. When a crystal is used, a capacitor must be connected

from this pin to ground (see Figure 5-9).

X2 31 33 O Crystal 2: Connection for other side of the crystal. When a crystal is used, a

capacitor must be connected from this pin to ground (see Figure 5-9). If X1/CLK is

driven from an external source, this pin must be left open.

RxDA 29 31 I Channel A receiver serial data input: The least significant bit is received first. See

note on drive levels at block diagram (Figure 1-1).

RxDB 5 5 I Channel B receiver serial data input: The least significant bit is received first. See

note on drive levels at block diagram (Figure 1-1).

TxDA 28 30 O Channel A transmitter serial data output: The least significant bit is transmitted first.

This output is held in the Mark condition when the transmitter is disabled, Idle or

when operating in local loopback mode. See note on drive levels at block diagram

(Figure 1-1).

TxDB 6 8 O Channel B transmitter serial data output: The least significant bit is transmitted first.

This output is held in the Mark condition when the transmitter is disabled, Idle, or

when operating in local loopback mode. See note on drive levels at block diagram

(Figure 1-1).

OP0 27 29 O Output 0: General purpose output or channel A request to send (RTSAN, active

LOW). Can be deactivated automatically on receive or transmit.

OP1 7 9 O Output 1: General-purpose output or channel B request to send (RTSBN, active

LOW). Can be deactivated automatically on receive or transmit.

OP2 26 28 O Output 2: General purpose output, or channel A transmitter 1× or 16× clock output,

or channel A receiver 1× clock output.

OP3 8 10 O Output 3: General purpose output or open-drain, active LOW counter/timer output or

channel B transmitter 1× clock output, or channel B receiver 1× clock output.

OP4 25 27 O Output 4: General purpose output or channel A open-drain, active LOW, RxA

interrupt ISR[1] output.

OP5 9 11 O Output 5: General-purpose output or channel B open-drain, active LOW, RxB

interrupt ISR[5] output.

OP6 24 26 O Output 6: General purpose output or channel A open-drain, active LOW, TxA

interrupt ISR[0] output.

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