TL28L92
www.ti.com
SLLS890B–AUGUST 2008–REVISED AUGUST 2009
Table 1-1. PIN DESCRIPTION FOR 80xxx INTERFACE
TERMINAL
TYPE DESCRIPTION
QFP (FR) QFN (RGZ)
NAME
PIN NO. PIN NO.
I/M 11 7 I Bus configuration: When HIGH or not connected configures the bus interface to the
conditions shown in this table.
D0, D1, 22, 12, 23, 14, I/O Data bus: Bidirectional 3-state data bus used to transfer commands, data and status
D2, D3, 21,13, 22,15, between the DUART and the CPU. D0 is the least significant bit.
D4, D5, 20, 14, 21, 16,
D6, D7 19, 15 20, 17
CEN 33 35 I Chip enable: active LOW input signal. When LOW, data transfers between the CPU
and the DUART are enabled on D0 to D7 as controlled by the WRN, RDN and A0 to
A3 inputs. When HIGH, places the D0 to D7 lines in the 3-state condition.
WRN 3 3 I Write strobe: When LOW and CEN is also LOW, the contents of the data bus is
loaded into the addressed register. The transfer occurs on the rising edge of the
signal.
RDN 4 4 I Read strobe: When LOW and CEN is also LOW, causes the contents of the
addressed register to be presented on the data bus. The read cycle begins on the
falling edge of RDN.
A0, A1, 40, 42, 44, 46, I Address inputs: Select the DUART internal registers and ports for read/write
A2, A3 44, 1 48, 1 operations.
RESET 32 34 I Reset: A HIGH level clears internal registers (SRA, SRB, IMR, ISR, OPR and
OPCR), puts OP0 to OP7 in the HIGH state, stops the counter/timer, and puts
channels A and B in the inactive state, with the TxDA and TxDB outputs in the mark
(HIGH) state. Sets MR pointer to MR1. See Figure 5-2.
INTRN 18 19 O Interrupt request: Active LOW, open-drain, output which signals the CPU that one or
more of the eight maskable interrupting conditions are true. This pin requires a
pull-up device.
X1/CLK 30 32 I Crystal 1: Crystal or external clock input. A crystal or clock of the specified limits
must be supplied at all times. When a crystal is used, a capacitor must be connected
from this pin to ground (see Figure 5-9).
X2 31 33 O Crystal 2: Connection for other side of the crystal. When a crystal is used, a
capacitor must be connected from this pin to ground (see Figure 5-9). If X1/CLK is
driven from an external source, this pin must be left open.
RxDA 29 31 I Channel A receiver serial data input: The least significant bit is received first. See
note on drive levels at block diagram (Figure 1-1).
RxDB 5 5 I Channel B receiver serial data input: The least significant bit is received first. See
note on drive levels at block diagram (Figure 1-1).
TxDA 28 30 O Channel A transmitter serial data output: The least significant bit is transmitted first.
This output is held in the Mark condition when the transmitter is disabled, Idle or
when operating in local loopback mode. See note on drive levels at block diagram
(Figure 1-1).
TxDB 6 8 O Channel B transmitter serial data output: The least significant bit is transmitted first.
This output is held in the Mark condition when the transmitter is disabled, Idle, or
when operating in local loopback mode. See note on drive levels at block diagram
(Figure 1-1).
OP0 27 29 O Output 0: General purpose output or channel A request to send (RTSAN, active
LOW). Can be deactivated automatically on receive or transmit.
OP1 7 9 O Output 1: General-purpose output or channel B request to send (RTSBN, active
LOW). Can be deactivated automatically on receive or transmit.
OP2 26 28 O Output 2: General purpose output, or channel A transmitter 1× or 16× clock output,
or channel A receiver 1× clock output.
OP3 8 10 O Output 3: General purpose output or open-drain, active LOW counter/timer output or
channel B transmitter 1× clock output, or channel B receiver 1× clock output.
OP4 25 27 O Output 4: General purpose output or channel A open-drain, active LOW, RxA
interrupt ISR[1] output.
OP5 9 11 O Output 5: General-purpose output or channel B open-drain, active LOW, RxB
interrupt ISR[5] output.
OP6 24 26 O Output 6: General purpose output or channel A open-drain, active LOW, TxA
interrupt ISR[0] output.
Copyright © 2008–2009, Texas Instruments Incorporated General Description 13
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