可重构SoC系统级设计与优化

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"System Level Design of Reconfigurable Systems-on-Chip" 是一本专注于硬件/软件协同设计在可重构SoC中的应用的书籍。随着对系统灵活性和计算能力的不断增长的需求，可重构性成为了SoC设计中的关键部分。当前的设计方法在处理由此引入的额外设计维度时提供有限的支持。书中强调了在系统层面需要更深入的支持，包括动态可重构功能块的识别和建模、高效的设计空间探索、分区和映射以及性能评估。系统级建模应包含如上下文切换和配置数据等开销影响，以便为决策提供可信的信息。该书由Nikolaos Oss VOROS和Konstantinos Masselos编著，包含了对现有C++语言（SystemC和OCAP-XL）扩展以支持可重构性的讨论，以及三个在无线和多媒体通信领域的案例研究，这些案例用于验证所提出方法的有效性。这些案例研究是验证和理解可重构SoC设计策略的重要实例。书中的内容可能涵盖以下知识点： 1. **可重构SoC的基本概念**：解释可重构SoC是如何通过改变其硬件结构来适应不同任务需求的，以提高效率和灵活性。 2. **硬件/软件协同设计**：探讨如何在系统级设计中结合硬件和软件的优化，以利用可重构性。 3. **设计空间探索**：介绍如何有效地搜索可行的设计解决方案，以满足可重构性的需求。 4. **分区和映射技术**：讲解如何将任务分配到SoC的不同部分，并将其映射到硬件资源上，以实现最佳性能。 5. **性能评估**：讨论评估可重构SoC性能的方法，包括考虑上下文切换和配置数据开销。 6. **SystemC和OCAP-XL的扩展**：说明如何扩展这两种编程语言，以支持可重构系统的建模和仿真。 7. **动态可重构功能块**：深入研究如何在系统层面识别和建模这些可以改变其功能的模块。 8. **案例研究**：通过无线和多媒体通信领域的实际应用场景，展示可重构SoC设计的挑战和解决方案。 9. **决策制定**：解释如何基于系统级建模的详细信息做出设计决策，确保可重构SoC在满足功能需求的同时，保持高性能和低功耗。这本书不仅对学术研究人员和工程师具有价值，也是理解和实践可重构SoC设计的宝贵资源，有助于推动未来SoC设计的发展。

. Introduction to Recon

urable Hardware 1

approach because it can be used to accelerate almost any

lication [1].

rocessor - the logic is next to the processor. Communication is

done usin

a protocol.

Attached processor - the logic is placed on some kind of I/O bus. With

the coprocessor and attached processor approaches, the speed

mprovement using the reconfigurable logic has to compensate for the

verhead of transferrin

the data. This usuall

happens in applications

here a hu

e amount of data has to be processed usin

a simple

algorithm that fits in the reconfigurable logic.

2.3 Static and dynamic reconfiguration

There are two basic reconfi

uration approaches:

static

namic

2.3.1 Static reconfi

uration

Static reconfiguration (often referred as compile time reconfiguration

)

the simplest and most common approach for implementing applications with

econfigurable logic. Static reconfiguration involves hardware changes at a

elativel

slow rate. It is a static implementation strate

where each

application consists of one confi

uration. The main ob

ective is to improve

the performance.

Configur

xecut

Figure 1-3

Principle of static reconfiguration

The distinctive feature of this confi

uration is that it consists of a sin

ystem-wide configuration. Prior to commencing an operation, the

reconfigurable resources are loaded with their respective configurations.

nce operation commences, the reconfigurable resources will remain in this

onfi

uration throu

hout the operation of the application. Thus hardware

resources remain static for the life of the desi

n (or application). This is

depicted in Figure 1-3. Much higher performance than with pure software

implementation (e.g. microprocessor approaches), cost advantage over

1. Introduction to Recon

urable Hardware 21

3. CLASSIFICATION OF RECONFIGURABLE

ARCHITECTURES

In this section reconfigurable hardware architectures are classified with

espect to several parameters. These parameters are described below:

•

ranular

of bu

blocks This refers to the levels of

manipulation of data. In this chapter we distinguish three types of

ranularity: fine-grain which corres

onds to bit-level mani

ulation of

ata

medium grain manipulating data with varying number of bits and

coarse-

rain

ranularit

which implies word level operations.

• Reconfiguration scheme Systems can be reconfigured statically or

ynamically. Dynamically reconfigurable systems permit the partial

econfiguration of certain logic blocks while others are performing

omputations. Staticall

reconfi

urable devices require execution

nterrupt.

•

oupling This refers to the degree of coupling with a host

micro

rocessor. In a

closely coupled

system reconfigurable units are

placed on the data path of the processor, acting as execution units.

Loosely coupled

stems act as a coprocessor. The

are connected to a

ost computer system through channels or some special-purpose

3.1 Classification with respect to building blocks

granularity

The granularity criterion reflects the smallest block of which a

econfi

urable device is made.

fine-grained

architectures, the basic programmed building block

usually consists of a combinatorial network and a few flip-flops. The logic

block can be programmed into a simple logic function, such as a 2-bit adder.

These blocks are connected throu

h a reconfi

urable interconnection

network. More complex operations can be constructed b

reconfi

urin

this

network. Commercially available Field Programmable Gate Arrays (FPGAs)

are based on fine grain architectures.

lthough highly flexible, these systems exhibit a low efficiency when it

omes to more specific tasks. For example, althou

h an 8-bit adder can be

mplemented in a fine-grained circuit, it will be inefficient, compared to a

econfigurable array of 8-bit adders, when performing an addition-intensive

task. An 8-bit adder will also occupy more space in the fine-grained

mplementation.

Chapter 1

econfigurable systems which use logic blocks of larger granularity are

categorized as

edium-grained

[

6, 7, 10, 11, 17]. For exam

le, Gar

[6] is

esigned to perform a number of different operations on up to four 2-bit

nputs. Another medium-

rained structure was desi

ned specificall

mplement multipliers of a configurable bit-width [7]. The logic block used

n the multiplier FPGA is capable of implementing a 4x4 multiplication. The

HESS architecture [11] also o

erates on 4-bit values, with each of its cells

actin

as a 4-bit ALU. The ma

or advanta

e of medium-

rained s

stems

when compared to the fine-

rained architecture is, that the

better utilize the

chip area, since they are optimized for the specific operations. However, a

rawback of this approach is represented in a high overhead when

synthesizing operations which are incompatible with the simplest logic bloc

architecture

Coarse-grained

architectures are primarily intended for the

mplementation of tasks dominated by word-width operations. Because the

logic blocks used are optimized for large computations, they will perform

hese operations much more quickl

(and consume less chip area) than a set

of smaller cells connected to form the same t

pe of structure. However,

because their composition is static, they are unable to leverage optimizations

n the size of operands. On the other hand, these coarse-grained architectures

can be much more efficient than finer-grained architectures for

mplementin

functions closer to their basic word size. An example of

coarse-grained system is the RaPiD architecture [4].

very coarse granularit

is the case when the simplest logic block is

based on an entire micro

rocessor with or without s

ecial accelerators.

Examples of such architectures are the REMARC [12] and RAW [13]

architectures.

3.2 Classification with respect to reconfiguration scheme

3.2.1 Stat

call

reconf

urable arch

tectures

raditional reconfigurable architectures are

tatically reconfigurable

which means that the reconfigurable resources are configured at the start of

execution and remain unchan

ed for the duration of the application. In orde

o reconfigure a statically reconfigurable architecture, the system has to be

alted while the reconfiguration is in progress and then restarted with the

ew configuration.

raditional FPGA architectures have primaril

been seriall

pro

rammed

sin

le-context devices, allowin

onl

one confi

uration to be loaded at a

ime. This type of FPGAs is programmed using a serial stream of

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