TPS65982BB：集成5V负载开关的双USB-PD海报控制器

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TI-TPS65982BB是一款高性能的电源管理集成电路，特别适用于USB-PD（Power Delivery）设备，其设计目标是为这些设备提供高效且灵活的充电解决方案。该芯片的核心功能包括： 1. **双USB Type-C接口**：集成了一个5V/3A的负载开关，确保了与VBUS之间的安全连接，并提供了过电流保护和过电压保护，以确保设备在不同条件下都能稳定工作。它还具备Slew-rate控制功能，能有效管理电压变化，防止瞬间电流冲击。 2. **快速USB吹速endpoint**：支持I2C（Inter-Integrated Circuit）通信协议，允许通过I2C接口实时更新USB Type-C端口的状态信息，增强了系统的可编程性和兼容性。这使得设计者可以轻松地监控和调整设备的行为。 3. **智能USBmux**：集成的USB多路复用器允许连接两个USB Type-C端口，这意味着一个设备可以同时支持多个USB设备或多个功率配置，增加了实用性。 4. **电源管理**：TPS65982BB可以从3.3V电源供电，这对于电池供电的系统来说是一个优点，因为它可以减少额外的电源转换步骤，提高能源效率。 5. **紧凑封装**：采用NFBGA（Non-Force Solder Ball Grid Array）封装，具有0.5mm间距，适合通过孔式安装，便于集成到各种设计中。 6. **广泛的应用领域**：该芯片适用于多种应用场合，如Docking systems（对接系统）、Charger adapters（充电适配器）、USB PD设备以及那些需要通过USB PD协议进行供电的设备，比如USB PD驱动的bus-powered devices（通过USB PD供电的设备），甚至包括DisplayPort和Thunderbolt接口的设备。 7. **重要注意事项**：文档末尾的重要通知包含了关于产品可用性、保修政策、安全性关键应用、知识产权声明以及其他免责声明，确保用户在使用时了解所有相关条款和限制。 TI-TPS65982BB是一款专为USB-PD设备设计的高效电源管理芯片，其集成的特性使其成为现代电子设备中实现高效充电和连接的理想选择。

TPS65982BB

SLVSER3A –NOVEMBER 2018–REVISED APRIL 2020

www.ti.com

Product Folder Links: TPS65982BB

(1) I/O buffers are not fail-safe to LDO_3V3. Therefore, VDDIO may power-up before LDO_3V3. When VDDIO powers up before LDO_3V3,

the I/Os shall not be driven high. When VDDIO is low and LDO_3V3 is high, the I/Os may be driven high.

6.5 Power Supply Characteristics

Recommended operating conditions; T

= –10 to +85°C unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

EXTERNAL

VIN_3V3 Input 3.3-V supply 2.85 3.3 3.45 V

VBUS Output DC bus voltage. 4 5 5.5 V

PP_5V0

5-V supply input to power VBUS. This supply

does not power the TPS65982BB

4.75 5 5.5 V

VDDIO

(1)

Optional supply for I/O cells 1.7 3.45 V

INTERNAL

VLDO_3V3

DC 3.3 V generated internally by either a switch

from VIN_3V3, an LDO from PP_CABLE, or an

LDO from VBUS

2.7 3.3 3.45 V

VLDO_1V8D DC 1.8 V generated for internal digital circuitry 1.7 1.8 1.9 V

VLDO_1V8A DC 1.8 V generated for internal analog circuitry 1.7 1.8 1.9 V

VLDO_BMC

DC voltage generated on LDO_BMC. Setting for

USB-PD.

1.05 1.125 1.2 V

IOUT_3V3 External DC current supplied by VOUT_3V3 100 mA

ILDO_1V8D

DC current supplied by LDO_1V8D. This is

intended for internal loads only but small external

loads may be added

50 mA

ILDO_1V8DEX External DC current supplied by LDO_1V8D 5 mA

ILDO_1V8A

DC current supplied by LDO_1V8A. This is

intended for internal loads only but small external

loads may be added

20 mA

ILDO_1V8AEX External DC current supplied by LDO_1V8A 5 mA

ILDO_BMC

DC current supplied by LDO_BMC. This is

intended for internal loads only

5 mA

ILDO_BMCEX External DC current supplied by LDO_BMC 0 mA

VFWD_DROP

Forward voltage drop across VIN_3V3 to

LDO_3V3 switch

LOAD

= 50 mA 25 60 90 mV

RIN_3V3

Input switch resistance from VIN_3V3 to

LDO_3V3

VIN_3V3

– V

LDO_3V3

> 50 mV 0.5 1.1 1.75 Ω

ROUT_3V3

Output switch resistance from VIN_3V3 to

VOUT_3V3

0.35 0.7 Ω

TR_OUT3V3

10-90% rise time on VOUT_3V3 from switch

enable

VOUT_3V3

= 1 μF 35 120 µs

TPS65982BB

www.ti.com

SLVSER3A –NOVEMBER 2018–REVISED APRIL 2020

Product Folder Links: TPS65982BB

6.6 Power Supervisor Characteristics

Recommended operating conditions; T

= –10 to +85°C unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

UV_LDO3V3

Undervoltage threshold for LDO_3V3. Locks out 1.8-V

LDOs

LDO_3V3 rising 2.2 2.325 2.45 V

UVH_LDO3V3 Undervoltage hysteresis for LDO_3V3 LDO_3V3 falling 20 80 150 mV

UV_5V0 Undervoltage threshold for PP_5V0 PP_5V0 rising 3.5 3.725 3.95 V

UVH_5V0 Undervoltage hysteresis for PP_P5V0 PP_5V0 falling 20 80 150 mV

OV_VBUS Overvoltage threshold for VBUS. VBUS rising 5 24 V

OVLSB_VBUS

Overvoltage threshold step for VBUS. This value is the

LSB of the programmable threshold

VBUS rising 328 mV

OVH_VBUS Overvoltage hysteresis for VBUS VBUS falling, % of OV_VBUS 0.9% 1.3% 1.7%

UV_VBUS Undervoltage threshold for VBUS. VBUS falling 2.5 18.21 V

UVLSB_VBUS

Undervoltage threshold step for VBUS. This value is the

LSB of the programmable threshold

VBUS falling 249 mV

UVH_VBUS Undervoltage hysteresis for VBUS VBUS rising, % of UV_VBUS 0.9% 1.3% 1.7%

(1) Application code can result in other power consumption measurements by adjusting enabled circuitry and clock rates. Application code

also provisions the wake-up mechanisms (for example, I

C activity and GPIO activity).

6.7 Power Consumption Characteristics

Recommended operating conditions; T

= 25°C (Room temperature) unless otherwise noted

(1)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

IVIN_3V3 in sleep

VIN_3V3 = VDDIO = 3.45 V, VBUS = 0, 100-kHz

oscillator running

71 µA

IVIN_3V3 idle

VIN_3V3 = VDDIO = 3.45 V, VBUS=0, 100-kHz

oscillator running,

48-MHz oscillator running

2.2 mA

IVIN_3V3 active

VIN_3V3 = VDDIO = 3.45 V, VBUS = 0, 100-kHz

Oscillator running,

48-MHz oscillator running

5.3 mA

(1) Maximum capacitance on VBUS when configured as a source must not exceed 12 µF.

(2) The current sense in the ADC does not accurately read below the current VREV5V0/RPP5V or VREVHV/RPPHV because of the

reverse blocking behavior. When reverse blocking is disabled, the values given for accuracy are valid.

6.8 Port-Power Switch Characteristics

Recommended operating conditions; T

= –10 to +85°C unless otherwise noted

PARAMETER TEST CONDITIONS

(1)

MIN TYP MAX UNIT

RPP5V PP_5V0 to VBUS power switch resistance 50 60 mΩ

IPP5VACT Active quiescent current from PP_5V0 1 mA

IPP5VSD Shutdown quiescent current from PP_5V0 100 μA

ILIMPP5V PP_5V0 current limit 3.019 3.355 3.69

IPP5V_ACC

(2)

PP_5V0 current sense accuracy

I = 100 mA, reverse current

blocking disabled

1.95 3 4.05 A/V

I = 200 mA 2.4 3 3.6 A/V

I = 500 mA 2.64 3 3.36 A/V

I ≥ 1 A 2.7 3 3.3 A/V

TON_5V

PP_5V0 path turn on time from enable to

VBUS = 95% of PP_5V0 voltage

Configured as a source or as a

sink with soft start disabled.

PP_5V0 = 5 V, CVBUS = 10 μF,

ILOAD = 100 mA

2.5 ms

VREV5V0

Reverse-current blocking voltage threshold for

PP_5V0 switches

2 6 10 mV

VSAFE0V

Voltage that is a safe 0 V per USB-PD

Specifications

0 0.8 V

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