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首页飞思卡尔Kinetis KL26低功耗MCU参考手册
“飞思卡尔(现为NXP)的Kinetis KL26参考手册,涵盖了32位超低功耗微控制器KL26系列的多个型号,包括MKL26Z32VFM4、MKL26Z128VLL4等。文档编号为KL26P121M48SF4RM,版本为Rev.3.2,发布于2013年10月。”
飞思卡尔(Freescale Semiconductor,现已被NXP Semiconductors收购)的Kinetis KL26系列是基于ARMCortex-M0+内核的32位微控制器,专为低功耗应用设计。该参考手册详细介绍了KL26子系列的各种功能和特性,为开发者提供了全面的技术指导。
手册的章节结构如下:
1. 关于本信息:
- 概览:解释了手册的目的,主要面向的读者群体,以及文档中使用的符号约定。
- 符号约定:包括数字系统、排版记号和特殊术语的说明。
2. 介绍:
- 概览:对Kinetis L系列的总体介绍,以及KL26子家族的特性和应用。
- 模块功能分类:
- ARM Cortex-M0+核心模块:描述了Cortex-M0+处理器的基本功能和特性。
- 系统模块:涵盖电源管理、中断控制器和其他系统级组件。
- 内存和内存接口:详细阐述闪存、SRAM及其他存储器类型和访问方式。
- 时钟:讨论了系统时钟源、时钟分频器和时钟管理。
- 安全与完整性模块:涉及到加密、安全启动等安全特性。
- 模拟模块:包括ADC、比较器等模拟电路功能。
- 计时器模块:如PWM、RTC等定时器功能的介绍。
- 通信接口:涵盖了I2C、SPI、UART等串行通信协议。
- 人机界面:如GPIO、LCD控制器等用于用户交互的硬件支持。
2.3 进一步介绍了可订购的部件号码和封装选项,这在选择和购买实际硬件时至关重要。
KL26微控制器以其低功耗特性,广泛应用于便携式设备、物联网(IoT)节点、传感器集线器以及能源管理应用。其丰富的外设集和高效的处理能力使其成为许多嵌入式设计的理想选择。通过深入阅读该参考手册,开发者可以了解如何充分利用这些特性来设计和优化他们的系统。
Section number Title Page
24.3.6 MCG Control 6 Register (MCG_C6)...........................................................................................................396
24.3.7 MCG Status Register (MCG_S)..................................................................................................................398
24.3.8 MCG Status and Control Register (MCG_SC)............................................................................................399
24.3.9 MCG Auto Trim Compare Value High Register (MCG_ATCVH)............................................................401
24.3.10 MCG Auto Trim Compare Value Low Register (MCG_ATCVL)..............................................................401
24.3.11 MCG Control 7 Register (MCG_C7)...........................................................................................................401
24.3.12 MCG Control 8 Register (MCG_C8)...........................................................................................................402
24.3.13 MCG Control 9 Register (MCG_C9)...........................................................................................................403
24.3.14 MCG Control 10 Register (MCG_C10).......................................................................................................403
24.4 Functional description...................................................................................................................................................403
24.4.1 MCG mode state diagram............................................................................................................................403
24.4.2 Low-power bit usage....................................................................................................................................408
24.4.3 MCG Internal Reference Clocks..................................................................................................................408
24.4.4 External Reference Clock............................................................................................................................409
24.4.5 MCG Fixed Frequency Clock .....................................................................................................................409
24.4.6 MCG PLL clock ..........................................................................................................................................410
24.4.7 MCG Auto TRIM (ATM)............................................................................................................................410
24.5 Initialization / Application information........................................................................................................................411
24.5.1 MCG module initialization sequence...........................................................................................................411
24.5.2 Using a 32.768 kHz reference......................................................................................................................414
24.5.3 MCG mode switching..................................................................................................................................414
Chapter 25
Oscillator (OSC)
25.1 Introduction...................................................................................................................................................................423
25.2 Features and Modes......................................................................................................................................................423
25.3 Block Diagram..............................................................................................................................................................424
25.4 OSC Signal Descriptions..............................................................................................................................................424
25.5 External Crystal / Resonator Connections....................................................................................................................425
25.6 External Clock Connections.........................................................................................................................................426
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16 Freescale Semiconductor, Inc.
Section number Title Page
25.7 Memory Map/Register Definitions...............................................................................................................................427
25.7.1 OSC Memory Map/Register Definition.......................................................................................................427
25.8 Functional Description..................................................................................................................................................428
25.8.1 OSC module states.......................................................................................................................................428
25.8.2 OSC module modes.....................................................................................................................................430
25.8.3 Counter.........................................................................................................................................................432
25.8.4 Reference clock pin requirements................................................................................................................432
25.9 Reset..............................................................................................................................................................................432
25.10 Low power modes operation.........................................................................................................................................433
25.11 Interrupts.......................................................................................................................................................................433
Chapter 26
Flash Memory Controller (FMC)
26.1 Introduction...................................................................................................................................................................435
26.1.1 Overview......................................................................................................................................................435
26.1.2 Features........................................................................................................................................................435
26.2 Modes of operation.......................................................................................................................................................436
26.3 External signal description............................................................................................................................................436
26.4 Memory map and register descriptions.........................................................................................................................436
26.5 Functional description...................................................................................................................................................436
Chapter 27
Flash Memory Module (FTFA)
27.1 Introduction...................................................................................................................................................................439
27.1.1 Features........................................................................................................................................................440
27.1.2 Block Diagram.............................................................................................................................................440
27.1.3 Glossary.......................................................................................................................................................441
27.2 External Signal Description..........................................................................................................................................442
27.3 Memory Map and Registers..........................................................................................................................................442
27.3.1 Flash Configuration Field Description.........................................................................................................442
KL26 Sub-Family Reference Manual, Rev. 3.2, October 2013
Freescale Semiconductor, Inc. 17
Section number Title Page
27.3.2 Program Flash IFR Map...............................................................................................................................443
27.3.3 Register Descriptions...................................................................................................................................444
27.4 Functional Description..................................................................................................................................................453
27.4.1 Flash Protection............................................................................................................................................453
27.4.2 Interrupts......................................................................................................................................................453
27.4.3 Flash Operation in Low-Power Modes........................................................................................................454
27.4.4 Functional Modes of Operation...................................................................................................................455
27.4.5 Flash Reads and Ignored Writes..................................................................................................................455
27.4.6 Read While Write (RWW)...........................................................................................................................455
27.4.7 Flash Program and Erase..............................................................................................................................455
27.4.8 Flash Command Operations.........................................................................................................................456
27.4.9 Margin Read Commands.............................................................................................................................460
27.4.10 Flash Command Description........................................................................................................................461
27.4.11 Security........................................................................................................................................................474
27.4.12 Reset Sequence............................................................................................................................................476
Chapter 28
Analog-to-digital converter (ADC)
28.1 Introduction...................................................................................................................................................................477
28.1.1 Features........................................................................................................................................................477
28.1.2 Block diagram..............................................................................................................................................478
28.2 ADC signal descriptions...............................................................................................................................................479
28.2.1 Analog Power (VDDA)...............................................................................................................................480
28.2.2 Analog Ground (VSSA)...............................................................................................................................480
28.2.3 Voltage Reference Select.............................................................................................................................480
28.2.4 Analog Channel Inputs (ADx).....................................................................................................................481
28.2.5 Differential Analog Channel Inputs (DADx)...............................................................................................481
28.3 Memory map and register definitions...........................................................................................................................481
28.3.1 ADC Status and Control Registers 1 (ADCx_SC1n)...................................................................................482
28.3.2 ADC Configuration Register 1 (ADCx_CFG1)...........................................................................................485
KL26 Sub-Family Reference Manual, Rev. 3.2, October 2013
18 Freescale Semiconductor, Inc.
Section number Title Page
28.3.3 ADC Configuration Register 2 (ADCx_CFG2)...........................................................................................487
28.3.4 ADC Data Result Register (ADCx_Rn).......................................................................................................488
28.3.5 Compare Value Registers (ADCx_CVn).....................................................................................................489
28.3.6 Status and Control Register 2 (ADCx_SC2)................................................................................................490
28.3.7 Status and Control Register 3 (ADCx_SC3)................................................................................................492
28.3.8 ADC Offset Correction Register (ADCx_OFS)...........................................................................................494
28.3.9 ADC Plus-Side Gain Register (ADCx_PG).................................................................................................494
28.3.10 ADC Minus-Side Gain Register (ADCx_MG)............................................................................................495
28.3.11 ADC Plus-Side General Calibration Value Register (ADCx_CLPD).........................................................495
28.3.12 ADC Plus-Side General Calibration Value Register (ADCx_CLPS)..........................................................496
28.3.13 ADC Plus-Side General Calibration Value Register (ADCx_CLP4)..........................................................496
28.3.14 ADC Plus-Side General Calibration Value Register (ADCx_CLP3)..........................................................497
28.3.15 ADC Plus-Side General Calibration Value Register (ADCx_CLP2)..........................................................497
28.3.16 ADC Plus-Side General Calibration Value Register (ADCx_CLP1)..........................................................498
28.3.17 ADC Plus-Side General Calibration Value Register (ADCx_CLP0)..........................................................498
28.3.18 ADC Minus-Side General Calibration Value Register (ADCx_CLMD).....................................................499
28.3.19 ADC Minus-Side General Calibration Value Register (ADCx_CLMS).....................................................499
28.3.20 ADC Minus-Side General Calibration Value Register (ADCx_CLM4).....................................................500
28.3.21 ADC Minus-Side General Calibration Value Register (ADCx_CLM3).....................................................500
28.3.22 ADC Minus-Side General Calibration Value Register (ADCx_CLM2).....................................................501
28.3.23 ADC Minus-Side General Calibration Value Register (ADCx_CLM1).....................................................501
28.3.24 ADC Minus-Side General Calibration Value Register (ADCx_CLM0).....................................................502
28.4 Functional description...................................................................................................................................................502
28.4.1 Clock select and divide control....................................................................................................................503
28.4.2 Voltage reference selection..........................................................................................................................504
28.4.3 Hardware trigger and channel selects..........................................................................................................504
28.4.4 Conversion control.......................................................................................................................................505
28.4.5 Automatic compare function........................................................................................................................513
28.4.6 Calibration function.....................................................................................................................................514
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Freescale Semiconductor, Inc. 19
Section number Title Page
28.4.7 User-defined offset function........................................................................................................................516
28.4.8 Temperature sensor......................................................................................................................................517
28.4.9 MCU wait mode operation...........................................................................................................................518
28.4.10 MCU Normal Stop mode operation.............................................................................................................518
28.4.11 MCU Low-Power Stop mode operation......................................................................................................519
28.5 Initialization information..............................................................................................................................................520
28.5.1 ADC module initialization example............................................................................................................520
28.6 Application information................................................................................................................................................522
28.6.1 External pins and routing.............................................................................................................................522
28.6.2 Sources of error............................................................................................................................................524
Chapter 29
Comparator (CMP)
29.1 Introduction...................................................................................................................................................................529
29.1.1 CMP features................................................................................................................................................529
29.1.2 6-bit DAC key features................................................................................................................................530
29.1.3 ANMUX key features..................................................................................................................................531
29.1.4 CMP, DAC and ANMUX diagram..............................................................................................................531
29.1.5 CMP block diagram.....................................................................................................................................532
29.2 Memory map/register definitions..................................................................................................................................534
29.2.1 CMP Control Register 0 (CMPx_CR0).......................................................................................................534
29.2.2 CMP Control Register 1 (CMPx_CR1).......................................................................................................535
29.2.3 CMP Filter Period Register (CMPx_FPR)...................................................................................................537
29.2.4 CMP Status and Control Register (CMPx_SCR).........................................................................................537
29.2.5 DAC Control Register (CMPx_DACCR)....................................................................................................538
29.2.6 MUX Control Register (CMPx_MUXCR)..................................................................................................539
29.3 Functional description...................................................................................................................................................540
29.3.1 CMP functional modes.................................................................................................................................540
29.3.2 Power modes................................................................................................................................................549
29.3.3 Startup and operation...................................................................................................................................550
KL26 Sub-Family Reference Manual, Rev. 3.2, October 2013
20 Freescale Semiconductor, Inc.
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