TI DS90C3202：3.3V FPD-Link接收器，高达9.45Gbps数据传输

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TI-DS90C3202是一款专为FPD-Link（Flexible Physical Display Interface）设计的高性能接收器，适用于各种高分辨率显示器应用，如液晶电视(LCD Monitors)、数字电视(Digital TVs)、QXGA面板及高清电视(HDTV)等。这款器件的工作电压为3.3V，支持8MHz到135MHz的宽广输入时钟范围，能够实现高达9.45Gbps的数据传输速率，非常适合低功耗、低电磁干扰(Low EMI)环境下的高速数据传输。 DS90C3202的核心功能包括： 1. **接口兼容性**：它旨在作为数字视频处理器和显示设备之间的桥梁，通过低功耗LVDS (Low Voltage Differential Signaling) 接口，提供高效的数据交换。LVDS支持30位、24位或18位颜色深度，适应不同彩色数据输入需求。 2. **多路数据处理**：该接收器能够处理多达10路的LVDS数据流，并将其转换为70位并行的LVCMOS/LVTTL数据，支持单像素或多像素接口，灵活适应各种显示分辨率，最高可达1920x1080p的高清画面。 3. **高速性能**：由于其高数据吞吐量，DS90C3202支持10Gbps以上的数据传输，这对于现代电子设备中的图像处理和显示传输至关重要。 4. **同步技术**：DS90C3202支持可编程的上升沿或下降沿时钟同步，以及可选的两线串行编程接口，允许进行精细的器件配置和控制，提高了系统灵活性。 5. **抗干扰特性**：通过采用散布谱时钟技术，DS90C3202能够有效减少电磁干扰，确保在嘈杂的电磁环境中稳定工作。 TI-DS90C3202是一款针对FPD-Link标准设计的高性能接收器，集成了高速数据传输、多路接口转换、低功耗设计以及高级同步技术，广泛应用于需要高质量显示性能和低辐射环境的显示设备中。

DS90C3202

www.ti.com

SNLS191D –APRIL 2005–REVISED APRIL 2013

Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

CMOS/TTL DC SPECIFICATIONS (Rx outputs, control inputs and outputs)

High Level Input Voltage 2.0 V

Low Level Input Voltage 0 0.8 V

High Level Output Voltage Rx clock out I

= −4 mA 2.4 V

Rx data out I

= −2 mA

Low Level Output Voltage Rx clock out I

= +4 mA 0.4 V

Rx data out I

= +2 mA

Input Clamp Voltage I

= −18 mA −0.8 −1.5 V

Input Current V

= V

+10 µA

= 0V −10 µA

Output Short Circuit Current V

OUT

= 0V −120 mA

LVDS RECEIVER DC SPECIFICATIONS

Differential Input High Threshold V

= +1.2V +100 mV

Differential Input Low Threshold −100 mV

Input Voltage Range (Single- 0 V

ended)

| Differential Input Voltage 0.200 0.600 V

Differential Common Mode 0.2 1.2 V

−0.1 V

Voltage

Input Current V

= +2.4V, V

= 3.6V ±10 µA

= 0V, V

= 3.6V ±10 µA

RECEIVER SUPPLY CURRENT

ICCRW Receiver Supply Current, Worst C

= 8 pF, f = 8 MHz 65 130 mA

Case Worst Case Pattern,

f = 135 MHz 375 550 mA

(Figure 4 , Figure 6) Default Register Settings

ICCRG Receiver Supply Current, C

= 8 pF, f = 8 MHz 55 120 mA

Incremental Test Pattern Worst Case Pattern,

f = 135 MHz 245 400 mA

(Figure 5 , Figure 6) Default Register Settings

ICCRZ Receiver Supply Current, Power PDWNB = Low, 2 mA

Down Receiver Outputs stay low during

Powerdown mode,

Default Register Settings

Product Folder Links: DS90C3202

DS90C3202

SNLS191D –APRIL 2005–REVISED APRIL 2013

www.ti.com

Receiver Switching Characteristics

(1)

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol Parameter Condition or Min Typ Max Unit

Reference

CLHT LVCMOS/LVTTL Low-to-High Transition Time, C

Rx clock out 1.45 2.10 ns

= 8pF, (Figure 7)

(2)

Rx data out 2.40 3.50 ns

bit [2] (RCLK)=0b (Default),

bit [1] (RXE) =0b (Default),

bit [0] (RXO) =0b (Default)

CHLT LVCMOS/LVTTL High-to-Low Transition Time, C

Rx clock out 1.35 2.20 ns

= 8pF, (Figure 7)

(2)

Rx data out 2.40 3.60 ns

bit [2] (RCLK)=0b (Default),

bit [1] (RXE) =0b (Default),

bit [0] (RXO) =0b (Default)

CLHT LVCMOS/LVTTL Low-to-High Transition Time, C

Rx clock out 2.45 ns

Programmable = 8pF, (Figure 7)

(2)

Rx data out 3.40 ns

adjustment Register addr 28d/1ch,

bit [2] (RCLK)=1b (Default),

bit [1] (RXE) =1b (Default),

bit [0] (RXO) =1b (Default)

CHLT LVCMOS/LVTTL High-to-Low Transition Time, C

Rx clock out 2.35 ns

Programmable = 8pF, (Figure 7)

(2)

Rx data out 3.40 ns

adjustment Register addr 28d/1ch,

bit [2] (RCLK)=0b (Default),

bit [1] (RXE) =0b (Default),

bit [0] (RXO) =0b (Default)

RCOP RCLK OUT Period (Figure 13, Figure 14)

(2)

8–135 MHz 7.4 T 125 ns

RCOH RCLK OUT High Time (Figure 13 , Figure 14) Rx clock out 0.4T 0.5T 0.6T ns

RCOL RCLK OUT Low Time (Figure 13 , Figure 14) Rx clock out 0.4T 0.5T 0.6T ns

RSRC RxOUT Setup to RCLK OUT (Figure 13, Figure 14)

(2) (3)

2.60 0.5T ns

RHRC RxOUT Hold to RCLK OUT (Figure 13 , Figure 14)

(2) (3)

3.60 0.5T ns

RSRC/RHRC Register addr 29d/1dh [2:1] = 01b, (Figure 15, Figure 16)

(4)

+1UI / -1UI ns

Programmable RSRC increased from default by 1UI

Adjustment RHRC decreased from default by 1UI

(4)

-1UI / +1UI ns

RSRC decreased from default by 1UI

RHRC increased from default by 1UI

(4)

+2UI / -2UI ns

RSRC increased from default by 2UI

RHRC decreased from default by 2UI

RPLLS Receiver Phase Lock Loop Set (Figure 8) 10 ms

RPDD Receiver Powerdown Delay (Figure 9) 100 ns

RPDL Receiver Propagation Delay — Latency (Figure 10) 4*RCLK ns

RITOL Receiver Input Tolerance V

= 1.25V, 0.25 UI

(Figure 12 Figure 18)

(2) (4)

= 350mV

(1) Typical values are given for V

= 3.3V and T

= +25°C.

(2) Specification is ensured by characterization.

(3) A Clock Unit Symbol (T) is defined as 1/ (Line rate of RCLK). E.g. For Line rate of RCLK at 85MHz, 1 T = 11.76ns

(4) A Unit Interval (UI) is defined as 1/7th of an ideal clock period (RCLK/7). E.g. For an 11.76ns clock period (85MHz), 1 UI = 1.68ns

Product Folder Links: DS90C3202

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