Hi3515
用户指南 目 录
文档版本 03 (2011-05-06)
海思专有和保密信息
版权所有 © 深圳市海思半导体有限公司
2-1
目 录
2 硬件特性.......................................................................................................................................2-7
2.1 管脚描述......................................................................................................................................................2-7
2.1.1 POWER 管脚.......................................................................................................................................2-8
2.1.2 SYS 管脚 ...........................................................................................................................................2-17
2.1.3 SIO 管脚............................................................................................................................................2-18
2.1.4 DAC 管脚..........................................................................................................................................2-18
2.1.5 DDR 管脚..........................................................................................................................................2-20
2.1.6 EBI 管脚 ............................................................................................................................................2-24
2.1.7 ETH 管脚...........................................................................................................................................2-26
2.1.8 I2C 管脚 ............................................................................................................................................2-27
2.1.9 SATA 管脚.........................................................................................................................................2-27
2.1.10 JTAG 管脚 .......................................................................................................................................2-28
2.1.11 UART 管脚 ......................................................................................................................................2-28
2.1.12 USB 管脚.........................................................................................................................................2-29
2.1.13 VO 管脚...........................................................................................................................................2-29
2.1.14 VI 管脚 ............................................................................................................................................2-30
2.2 软件复用管脚描述....................................................................................................................................2-32
2.3 硬件管脚复用描述....................................................................................................................................2-39
2.4 IO Config（管脚复用控制）寄存器概览.................................................................................................2-40
2.5 上下电顺序推荐........................................................................................................................................2-65
2.6 外部中断....................................................................................................................................................2-66
2.7 电气特性....................................................................................................................................................2-66
2.7.1 DC/AC 参数 ......................................................................................................................................2-66
2.7.2 推荐工作条件...................................................................................................................................2-67
2.8 PCB 布线建议 ............................................................................................................................................2-68
2.9 时序规格....................................................................................................................................................2-68
2.9.1 时序图例 ..........................................................................................................................................2-68
2.9.2 DDR2 接口时序 ................................................................................................................................2-68
2.9.3 ETH 接口时序...................................................................................................................................2-71
2.9.4 VI 接口时序 ......................................................................................................................................2-74
