"BCM2837- 树莓派芯片手册1；1.2.1-8.4.1详解"

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The BCM2837 is a chip used in the Raspberry Pi, and this manual serves as a comprehensive guide to its functionality and specifications. The manual covers a wide range of topics, including the architecture of the chip, its peripherals, and important errata information. The manual begins with an overview of the BCM2837, detailing its architecture and key features. It covers important aspects such as the memory map, GPIO, and DMA controller. This sets the stage for more in-depth discussions on the specific peripherals of the chip. The manual delves into the specifics of various peripherals, including the UART, SPI, I2C, and PWM. Each section provides detailed information on the operation and configuration of these peripherals, enabling users to make the most of the chip's capabilities. In addition to discussing the peripherals, the manual also highlights important errata information. This includes a reference to an updated document that incorporates valuable errata information. By acknowledging the existence of errata and providing a resource for updated information, the manual ensures that users have access to the most accurate and reliable information about the chip. Throughout the manual, the level of detail is impressive, catering to both novice and experienced users. The inclusion of specific revision information, such as the revision done by a professor at Stanford, adds to the credibility of the manual. Overall, the BCM2837 manual is a valuable resource for anyone looking to understand and utilize the capabilities of this chip. Its comprehensive coverage of the chip's architecture, peripherals, and errata information makes it an essential reference for developers, hobbyists, and anyone else working with the Raspberry Pi. By combining technical detail with practical insight, the manual empowers users to harness the full potential of the BCM2837 chip.

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 16

AUX_MU_SCRATCH Register (0x7E21 505C)

YNOPSIS

The

AUX_MU_SCRATCH

is a single byte storage.

Bit(s) Field Name Description Type

Reset

31:8

Reserved, write zero, read as don’t care

7:0 Scratch

One whole byte extra on top of the 134217728

provided by the SDC

R/W 0

AUX_MU_CNTL_REG Register (0x7E21 5060)

YNOPSIS

The

AUX_MU_CNTL_REG

provides access to some extra useful and nice features not

found on a normal 16550 UART .

Bit(s) Field Name Description Type

Reset

31:8

Reserved, write zero, read as don’t care

CTS assert

level

This bit allows one to invert the CTS auto flow

operation polarity.

If set the CTS auto flow assert level is low*

If clear the CTS auto flow assert level is high*

R/W 0

RTS assert

level

This bit allows one to invert the RTS auto flow

operation polarity.

If set the RTS auto flow assert level is low*

If clear the RTS auto flow assert level is high*

R/W 0

5:4

RTS AUTO

flow level

These two bits specify at what receiver FIFO level the

RTS line is de-asserted in auto-flow mode.

00 : De-assert RTS when the receive FIFO has 3

empty spaces left.

01 : De-assert RTS when the receive FIFO has 2

empty spaces left.

10 : De-assert RTS when the receive FIFO has 1

empty space left.

11 : De-assert RTS when the receive FIFO has 4

empty spaces left.

R/W 0

Enable

transmit Auto

flow-control

using CTS

If this bit is set the transmitter will stop if the CTS

line is de-asserted.

If this bit is clear the transmitter will ignore the status

of the CTS line

R/W 0

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 17

Enable receive

Auto flow-

control using

RTS

If this bit is set the RTS line will de-assert if the

receive FIFO reaches it 'auto flow' level. In fact the

RTS line will behave as an RTR (Ready To Receive)

line.

If this bit is clear the RTS line is controlled by the

AUX_MU_MCR_REG register bit 1.

R/W 0

Transmitter

enable

If this bit is set the mini UART transmitter is enabled.

If this bit is clear the mini UART transmitter is

disabled

R/W 1

Receiver

enable

If this bit is set the mini UART receiver is enabled.

If this bit is clear the mini UART receiver is disabled

R/W 1

Auto flow control

Automatic flow control can be enabled independent for the receiver and the transmitter.

CTS auto flow control impacts the transmitter only. The transmitter will not send out new

symbols when the CTS line is de-asserted. Any symbols in progress of transmission when

the CTS line becomes de-asserted will be finished.

RTS auto flow control impacts the receiver only. In fact the name RTS for the control line is

incorrect and should be RTR (Ready to Receive). The receiver will de-asserted the RTS

(RTR) line when its receive FIFO has a number of empty spaces left. Normally 3 empty

spaces should be enough.

If looping back a mini UART using full auto flow control the logic is fast enough to allow

the RTS auto flow level of '10' (De-assert RTS when the receive FIFO has 1 empty space

left).

Auto flow polarity

To offer full flexibility the polarity of the CTS and RTS (RTR) lines can be programmed.

This should allow the mini UART to interface with any existing hardware flow control

available.

Receiver enable

If this bit is cleared no new symbols will be accepted by the receiver. Any symbols in

progress of reception will be finished.

Transmitter enable

If this bit is cleared no new symbols will be sent by the transmitter. Any symbols in

progress of transmis sion will be finished.

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 20

2.3 Universal SPI Master (2x)

The two universal SPI masters are secondary low throughput

SPI interfaces. Like the UART

the devices needs to be enabled before they can be used. Each SPI master has the following

features:

• Single beat bit length between 1 and 32 bits.

• Single beat variable bit length between 1 and 24 bits

• Multi beat infinite bit length.

• 3 independent chip selects per master.

• 4 entries 32-bit wide transmit and receive FIFOs.

• Data out on rising or falling clock edge.

• Data in on rising or falling clock edge.

• Clock inversion (Idle high or idle low).

• Wide clocking range.

• Programmable data out hold time.

• Shift in/out MS or LS bit first

A major issue with an SPI interface is that there is no SPI standard in any form. Because the

SPI interface has been around for a long time some pseudo-standard rules have appeared

mostly when interfacing with memory devices. The universal SPI master has been developed

to work even with the most 'non-standard' SPI devices.

2.3.1 SPI implementation details

The following diagrams shows a typical SPI access cycle. In this case we have 8 SPI clocks.

1 Bit time

Set-up Operate

Hold

(optional)

Idle

Clk

Cs_n

One bit time before any clock edge changes the CS_n will go low. This makes sure that the

MOSI signal has a full bit-time of set-up against any changing clock edges.

The operation normally ends after the last clock cycle. Note that at the end there is one half-

bit time where the clock does not change but which still is part of the operation cycle.

There is an option to add a half bit cycle hold time. This makes sure that any MISO data has

at least a full SPI bit time to arrive. (Without this hold time, data clocked out of the SPI

device on the last clock edge would have only half a bit time to arrive).

Again the SPIs themselves have no throughput limitations in fact they can run with an SPI clock of 125 MHz.

But doing so requires significant CPU involvement as they have shallow FIFOs and no DMA support.

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