TI DM385 & DM388 DaVinci 数字媒体处理器：高性能SoC

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"TI的DM385和DM388是基于DaVinci™技术的高性能数字媒体处理器，这两款SOC芯片集成了强大的ARM Cortex-A8内核，最高频率可达1GHz，专为高清视频处理和多媒体应用设计。它们支持多种编码、解码和转码操作，包括H.264 BP/MP/HP、MPEG-2、VC-1、MPEG-4 SP/ASP以及JPEG/MJPEG等格式。DM388还额外配备了一个第四代运动补偿噪声过滤器，进一步提升视频处理性能。" DM385和DM388数字媒体处理器是德州仪器(TI)推出的高集成度系统级芯片，其中包含一个1000MHz的ARM Cortex-A8 RISC处理器，可提供高达2000 MIPS的处理能力。这款内核基于ARMv7架构，具备指令和数据的双发、超标量处理能力，支持小端（Little Endian）模式，并集成了NEON多媒体架构，用于增强其在整数和浮点运算上的性能。此外，Jazelle® RCT执行环境使DM385和DM388能够快速运行Java应用程序。 DM385和DM388的关键特性之一是高清视频处理子系统（HDVPSS），该子系统由媒体控制器管理，可以处理两个165-MHz的高清视频输入，同时具有32KB的指令缓存和数据缓存，确保了高速数据处理。DM388还额外增加了高级功能，例如第四代运动补偿噪声过滤器，能有效提高视频质量，尤其在低光照条件下的表现。两款处理器均支持高清视频编码和解码，适用于多样的多媒体应用场景，如安防监控、视频会议、数字标牌、家庭娱乐系统等。DM388的增强特性使得它在处理复杂视频任务时更具优势，例如视频转码和噪声抑制。 DM385和DM388是针对高清晰度视频处理需求而设计的先进芯片，它们将强大的CPU性能与专门的视频处理硬件相结合，为开发者提供了高效的平台，以实现各种复杂的多媒体解决方案。对于需要高性能、低功耗和灵活编码解码能力的应用来说，DM385和DM388是理想的选择。

DM385, DM388

SPRS821D –MARCH 2013–REVISED DECEMBER 2013

www.ti.com

Table 2-3. L3 Memory Map (continued)

START ADDRESS END ADDRESS

SIZE DESCRIPTION

(HEX) (HEX)

0x47C0_C000 0x47C0_C3FF 1KB Reserved

0x47C0_C400 0x47C0_C7FF 1KB DDR PHY Registers

0x47C0_C800 0x47C0_CBFF 1KB Reserved

0x47C0_CC00 0x47C0_CFFF 1KB Reserved

0x47C0_D000 0x47FF FFFF 4052KB Reserved

0x4800_0000 0x48FF_FFFF 16MB L4 Slow Peripheral Domain

(see Table 2-5)

0x4900_0000 0x490F_FFFF 1MB EDMA TPCC Registers

0x4910_0000 0x497F_FFFF 7MB Reserved

0x4980_0000 0x498F_FFFF 1MB EDMA TPTC0 Registers

0x4990_0000 0x499F_FFFF 1MB EDMA TPTC1 Registers

0x49A0_0000 0x49AF_FFFF 1MB EDMA TPTC2 Registers

0x49B0_0000 0x49BF_FFFF 1MB EDMA TPTC3 Registers

0x49C0_0000 0x49FF_FFFF 4MB Reserved

0x4A00_0000 0x4AFF_FFFF 16MB L4 Fast Peripheral Domain

(see Table 2-4)

0x4B00_0000 0x4BFF_FFFF 16MB Emulation Subsystem

0x4C00_0000 0x4CFF_FFFF 16MB DDR Registers

0x4D00_0000 0x4DFF_FFFF 16MB Reserved

0x4E00_0000 0x4FFF_FFFF 32MB DDR DMM Registers

0x5000_0000 0x50FF_FFFF 16MB GPMC Registers

0x5100_0000 0x51FF_FFFF 16MB PCIE Registers

0x5200_0000 0x54FF_FFFF 48MB Reserved

0x5500_0000 0x55FF_FFFF 16MB Media Controller

0x5600_0000 0x56FF_FFFF 16MB Reserved

0x5700_0000 0x57FF_FFFF 16MB Reserved

0x5800_0000 0x58FF_FFFF 16MB HDVICP2 Configuration

0x5900_0000 0x59FF_FFFF 16MB HDVICP2 SL2

0x5A00_0000 0x5BFF_FFFF 32MB Reserved

0x5C00_0000 0x5DFF_FFFF 32MB ISS

0x5E00_0000 0x5FFF_FFFF 32MB Reserved

0x6000_0000 0x7FFF_FFFF 512MB DDR DMM Tiler Window (see Table 2-6)

0x8000_0000 0xFFFF_FFFF 2GB DDR

0x1 0000 0000 0x1 FFFF FFFF 4GB DDR DMM Tiler Extended Address Map

(ISS and HDVPSS only) [see Table 2-6]

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Product Folder Links: DM385 DM388

DM385, DM388

SPRS821D –MARCH 2013–REVISED DECEMBER 2013

www.ti.com

2.10.2.2 L4 Slow Peripheral Memory Map

Table 2-5. L4 Slow Peripheral Memory Map

Cortex-A8 and L3 Masters

SIZE DEVICE NAME

START ADDRESS END ADDRESS

(HEX) (HEX)

0x4800_0000 0x4800_07FF 2KB L4 Slow Configuration – Address/Protection (AP)

0x4800_0800 0x4800_0FFF 2KB L4 Slow Configuration – Link Agent (LA)

0x4800_1000 0x4800_13FF 1KB L4 Slow Configuration – Initiator Port (IP0)

0x4800_1400 0x4800_17FF 1KB L4 Slow Configuration – Initiator Port (IP1)

0x4800_1800 0x4800_1FFF 2KB Reserved

0x4800_2000 0x4800_7FFF 24KB Reserved

0x4800_8000 0x4800_8FFF 32KB Reserved

0x4801_0000 0x4801_0FFF 4KB Reserved

0x4801_1000 0x4801_1FFF 4KB Reserved

0x4801_2000 0x4801_FFFF 56KB Reserved

0x4802_0000 0x4802_0FFF 4KB UART0 Peripheral Registers

0x4802_1000 0x4802_1FFF 4KB UART0 Interconnect Registers

0x4802_2000 0x4802_2FFF 4KB UART1 Peripheral Registers

0x4802_3000 0x4802_3FFF 4KB UART1 Interconnect Registers

0x4802_4000 0x4802_4FFF 4KB UART2 Peripheral Registers

0x4802_5000 0x4802_5FFF 4KB UART2 Interconnect Registers

0x4802_6000 0x4802_7FFF 8KB Reserved

0x4802_8000 0x4802_8FFF 4KB I2C0 Peripheral Registers

0x4802_9000 0x4802_9FFF 4KB I2C0 Interconnect Registers

0x4802_A000 0x4802_AFFF 4KB I2C1 Peripheral Registers

0x4802_B000 0x4802_BFFF 4KB I2C1 Interconnect Registers

0x4802_C000 0x4802_DFFF 8KB Reserved

0x4802_E000 0x4802_EFFF 4KB TIMER1 Peripheral Registers

0x4802_F000 0x4802_FFFF 4KB TIMER1 Interconnect Registers

0x4803_0000 0x4803_0FFF 4KB SPI0 Peripheral Registers

0x4803_1000 0x4803_1FFF 4KB SPI0 Interconnect Registers

0x4803_2000 0x4803_2FFF 4KB GPIO0 Peripheral Registers

0x4803_3000 0x4803_3FFF 4KB GPIO0 Interconnect Registers

0x4803_4000 0x4803_7FFF 16KB Reserved

0x4803_8000 0x4803_9FFF 8KB McASP0 CFG Peripheral Registers

0x4803_A000 0x4803_AFFF 4KB McASP0 CFG Interconnect Registers

0x4803_B000 0x4803_BFFF 4KB Reserved

0x4803_C000 0x4803_DFFF 8KB McASP1 CFG Peripheral Registers

0x4803_E000 0x4803_EFFF 4KB McASP1 CFG Interconnect Registers

0x4803_F000 0x4803_FFFF 4KB Reserved

0x4804_0000 0x4804_0FFF 4KB TIMER2 Peripheral Registers

0x4804_1000 0x4804_1FFF 4KB TIMER2 Interconnect Registers

0x4804_2000 0x4804_2FFF 4KB TIMER3 Peripheral Registers

0x4804_3000 0x4804_3FFF 4KB TIMER3 Interconnect Registers

0x4804_4000 0x4804_4FFF 4KB TIMER4 Peripheral Registers

0x4804_5000 0x4804_5FFF 4KB TIMER4 Interconnect Registers

0x4804_6000 0x4804_6FFF 4KB TIMER5 Peripheral Registers

0x4804_7000 0x4804_7FFF 4KB TIMER5 Interconnect Registers

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Product Folder Links: DM385 DM388

DM385, DM388

www.ti.com

SPRS821D –MARCH 2013–REVISED DECEMBER 2013

Table 2-5. L4 Slow Peripheral Memory Map (continued)

Cortex-A8 and L3 Masters

SIZE DEVICE NAME

START ADDRESS END ADDRESS

(HEX) (HEX)

0x4804_8000 0x4804_8FFF 4KB TIMER6 Peripheral Registers

0x4804_9000 0x4804_9FFF 4KB TIMER6 Interconnect Registers

0x4804_A000 0x4804_AFFF 4KB TIMER7 Peripheral Registers

0x4804_B000 0x4804_BFFF 4KB TIMER7 Interconnect Registers

0x4804_C000 0x4804_CFFF 4KB GPIO1 Peripheral Registers

0x4804_D000 0x4804_DFFF 4KB GPIO1 Interconnect Registers

0x4804_E000 0x4804_FFFF 8KB Reserved

0x4805_0000 0x4805_1FFF 8KB Reserved

0x4805_2000 0x4805_2FFF 4KB Reserved

0x4805_3000 0x4805_FFFF 52KB Reserved

0x4806_0000 0x4806_FFFF 64KB MMC/SD/SDIO0 Peripheral Registers

0x4807_0000 0x4807_0FFF 4KB MMC/SD/SDIO0 Interconnect Registers

0x4807_1000 0x4807_FFFF 60KB Reserved

0x4808_0000 0x4808_FFFF 64KB ELM Peripheral Registers

0x4809_0000 0x4809_0FFF 4KB ELM Interconnect Registers

0x4809_1000 0x4809_FFFF 60KB Reserved

0x480A_0000 0x480A_FFFF 64KB Reserved

0x480B_0000 0x480B_0FFF 4KB Reserved

0x480B_1000 0x480B_FFFF 60KB Reserved

0x480C_0000 0x480C_0FFF 4KB RTC Peripheral Registers

0x480C_1000 0x480C_1FFF 4KB RTC Interconnect Registers

0x480C_2000 0x480C_3FFF 8KB Reserved

0x480C_4000 0x480C_7FFF 16KB Reserved

0x480C_8000 0x480C_8FFF 4KB Mailbox Peripheral Registers

0x480C_9000 0x480C_9FFF 4KB Mailbox Interconnect Registers

0x480C_A000 0x480C_AFFF 4KB Spinlock Peripheral Registers

0x480C_B000 0x480C_BFFF 4KB Spinlock Interconnect Registers

0x480C_C000 0x480F_FFFF 208KB Reserved

0x4810_0000 0x4811_FFFF 128KB HDVPSS Peripheral Registers

0x4812_0000 0x4812_0FFF 4KB HDVPSS Interconnect Registers

0x4812_1000 0x4812_1FFF 4KB Reserved

0x4812_2000 0x4812_2FFF 4KB HDMI Peripheral Registers

0x4812_3000 0x4812_3FFF 4KB HDMI Interconnect Registers

0x4812_4000 0x4813_FFFF 112KB Reserved

0x4814_0000 0x4815_FFFF 128KB Control Module Peripheral Registers

0x4816_0000 0x4816_0FFF 4KB Control Module Interconnect Registers

0x4816_1000 0x4817_FFFF 124KB Reserved

0x4818_0000 0x4818_2FFF 12KB PRCM Peripheral Registers

0x4818_3000 0x4818_3FFF 4KB PRCM Interconnect Registers

0x4818_4000 0x4818_7FFF 16KB Reserved

0x4818_8000 0x4818_8FFF 4KB SmartReflex0 Peripheral Registers

0x4818_9000 0x4818_9FFF 4KB SmartReflex0 Interconnect Registers

0x4818_A000 0x4818_AFFF 4KB SmartReflex1 Peripheral Registers

0x4818_B000 0x4818_BFFF 4KB SmartReflex1 Interconnect Registers

0x4818_C000 0x4818_CFFF 4KB OCP Watchpoint Peripheral Registers

0x4818_D000 0x4818_DFFF 4KB OCP Watchpoint Interconnect Registers

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Product Folder Links: DM385 DM388

DM385, DM388

SPRS821D –MARCH 2013–REVISED DECEMBER 2013

www.ti.com

Table 2-5. L4 Slow Peripheral Memory Map (continued)

Cortex-A8 and L3 Masters

SIZE DEVICE NAME

START ADDRESS END ADDRESS

(HEX) (HEX)

0x4818_E000 0x4818_EFFF 4KB Reserved

0x4818_F000 0x4818_FFFF 4KB Reserved

0x4819_0000 0x4819_3FFF 16KB Reserved

0x4819_4000 0x4819_BFFF 32KB Reserved

0x4819_C000 0x481F_FFFF 400KB Reserved

0x4819_C000 0x4819_CFFF 4KB I2C2 Peripheral Registers

0x4819_D000 0x4819_DFFF 4KB I2C2 Interconnect Registers

0x4819_E000 0x4819_EFFF 4KB I2C3 Peripheral Registers

0x4819_F000 0x4819_FFFF 4KB I2C3 Interconnect Registers

0x481A_0000 0x481A_0FFF 4KB SPI1 Peripheral Registers

0x481A_1000 0x481A_1FFF 4KB SPI1 Interconnect Registers

0x481A_2000 0x481A_2FFF 4KB SPI2 Peripheral Registers

0x481A_3000 0x481A_3FFF 4KB SPI2 Interconnect Registers

0x481A_4000 0x481A_4FFF 4KB SPI3 Peripheral Registers

0x481A_5000 0x481A_5FFF 4KB SPI3 Interconnect Registers

0x481A_6000 0x481A_6FFF 4KB Reserved

0x481A_7000 0x481A_7FFF 4KB Reserved

0x481A_8000 0x481A_8FFF 4KB Reserved

0x481A_9000 0x481A_9FFF 4KB Reserved

0x481A_A000 0x481A_AFFF 4KB Reserved

0x481A_B000 0x481A_BFFF 4KB Reserved

0x481A_C000 0x481A_CFFF 4KB GPIO2 Peripheral Registers

0x481A_D000 0x481A_DFFF 4KB GPIO2 Interconnect Registers

0x481A_E000 0x481A_EFFF 4KB GPIO3 Peripheral Registers

0x481A_F000 0x481A_FFFF 4KB GPIO3 Interconnect Registers

0x481B_0000 0x481B_FFFF 64KB Reserved

0x481C_0000 0x481C_0FFF 4KB Reserved

0x481C_1000 0x481C_1FFF 4KB TIMER8 Peripheral Registers

0x481C_2000 0x481C_2FFF 4KB TIMER8 Interconnect Registers

0x481C_3000 0x481C_3FFF 4KB SYNCTIMER32K Peripheral Registers

0x481C_4000 0x481C_4FFF 4KB SYNCTIMER32K Interconnect Registers

0x481C_5000 0x481C_5FFF 4KB PLLSS Peripheral Registers

0x481C_6000 0x481C_6FFF 4KB PLLSS Interconnect Registers

0x481C_7000 0x481C_7FFF 4KB WDT0 Peripheral Registers

0x481C_8000 0x481C_8FFF 4KB WDT0 Interconnect Registers

0x481C_9000 0x481C_9FFF 8KB Reserved

0x481C_A000 0x481C_BFFF 8KB Reserved

0x481C_C000 0x481C_DFFF 8KB Reserved

0x481C_E000 0x481C_FFFF 8KB Reserved

0x481D_0000 0x481D_1FFF 8KB Reserved

0x481D_2000 0x481D_3FFF 8KB Reserved

0x481D_4000 0x481D_5FFF 8KB Reserved

0x481D_6000 0x481D_6FFF 4KB Reserved

0x481D_7000 0x481D_7FFF 4KB Reserved

0x481D_8000 0x481E_7FFF 64KB MMC/SD/SDIO1 Peripheral Registers

0x481E_8000 0x481E_8FFF 4KB MMC/SD/SDIO1 Interconnect Registers

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Product Folder Links: DM385 DM388

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