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Freescale MPC5604B/C 微控制器参考手册
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"飞思卡尔MPC5604单片机使用及配置手册"
飞思卡尔(现为恩智浦半导体的一部分)的MPC5604是一款高性能的32位微控制器,专为需要复杂控制功能的应用设计。该手册详细阐述了MPC5604B/C微控制器的使用和配置,适用于那些需要深入了解该芯片特性和功能的工程师。
MPC5604BCRM参考手册包括两个主要部分:MPC5604B/C参考手册的增补文档(Rev.1)和MPC5604B/C参考手册本身(Rev.8.1)。手册的增补文档提供了对原始参考手册的修正和更新,确保用户获取到最新的信息。所有修订项按照版本号分组,方便用户查找。
手册内容涵盖:
1. **概述**:介绍MPC5604B/C的主要特性,如其32位处理器核心、内存结构、外设接口等。
2. **硬件描述**:详细列出芯片的物理布局,包括引脚定义、电源管理、时钟系统和封装信息。
3. **处理器核心**:详述内嵌的处理器架构,如指令集、中断系统、调试接口等。
4. **存储器**:包括闪存、SRAM和其他类型的存储配置和操作。
5. **外设**:涵盖各种内置的外设模块,如ADC、PWM、CAN总线、SPI、I2C、UART等,以及它们的使用方法和配置选项。
6. **系统控制**:描述电源管理、复位、时钟控制等功能。
7. **开发工具**:提供编程和调试工具的信息,包括IDE、编译器、仿真器等。
8. **应用示例**:提供实际应用场景中的配置实例,帮助用户理解和应用。
9. **故障排查与诊断**:给出常见问题的解决方法和错误代码的解释。
10. **安全特性**:如果有的话,介绍MPC5604的安全特性,如加密和安全启动等。
11. **修订历史**:记录每次更新的详细内容,以便跟踪变化。
为了确保获取最新信息,用户应定期访问飞思卡尔(Freescale Semiconductor,现恩智浦半导体)的官方网站,查看MPC5604B/C微控制器参考手册的最新修订版。
该手册对于那些在汽车电子、工业自动化、电力系统和其他需要精确控制的领域使用MPC5604B/C微控制器的工程师来说,是一份不可或缺的技术参考资料。通过深入学习和实践,工程师可以充分利用MPC5604B/C的强大功能,实现高效且可靠的系统设计。
MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 11
22.1.2 FlexCAN module features ............................................................................................424
22.1.3 Modes of operation .......................................................................................................425
22.2 External signal description ............................................................................................................425
22.2.1 Overview ......................................................................................................................425
22.2.2 Signal descriptions ........................................................................................................426
22.3 Memory map and register description ...........................................................................................426
22.3.1 FlexCAN memory mapping .........................................................................................426
22.3.2 Message buffer structure ..............................................................................................428
22.3.3 Rx FIFO structure .........................................................................................................431
22.3.4 Register description ......................................................................................................433
22.4 Functional description ...................................................................................................................451
22.4.1 Overview ......................................................................................................................451
22.4.2 Local priority transmission ...........................................................................................452
22.4.3 Transmit process ...........................................................................................................452
22.4.4 Arbitration process .......................................................................................................453
22.4.5 Receive process ............................................................................................................454
22.4.6 Matching process ..........................................................................................................455
22.4.7 Data coherence .............................................................................................................456
22.4.8 Rx FIFO ........................................................................................................................459
22.4.9 CAN protocol related features ......................................................................................460
22.4.10 Modes of operation details ...........................................................................................464
22.4.11 Interrupts .......................................................................................................................465
22.4.12 Bus interface .................................................................................................................465
22.5 Initialization/Application information ...........................................................................................466
22.5.1 FlexCAN initialization sequence ..................................................................................466
22.5.2 FlexCAN addressing and SRAM size configurations ..................................................467
Chapter 23
Deserial Serial Peripheral Interface (DSPI)
23.1 Introduction ...................................................................................................................................469
23.2 Features .........................................................................................................................................470
23.3 Modes of operation ........................................................................................................................471
23.3.1 Master mode .................................................................................................................471
23.3.2 Slave mode ...................................................................................................................471
23.3.3 Module Disable mode ...................................................................................................471
23.3.4 Debug mode ..................................................................................................................472
23.4 External signal description ............................................................................................................472
23.4.1 Signal overview ............................................................................................................472
23.4.2 Signal names and descriptions ......................................................................................472
23.5 Memory map and register description ...........................................................................................474
23.5.1 Memory map ................................................................................................................474
23.5.2 DSPI Module Configuration Register (DSPIx_MCR) .................................................475
23.5.3 DSPI Transfer Count Register (DSPIx_TCR) ..............................................................478
23.5.4 DSPI Clock and Transfer Attributes Registers 0–5 (DSPIx_CTARn) .........................478
23.5.5 DSPI Status Register (DSPIx_SR) ...............................................................................486
MPC5604B/C Microcontroller Reference Manual, Rev. 8
12 Freescale Semiconductor
23.5.6 DSPI Interrupt Request Enable Register (DSPIx_RSER) ............................................488
23.5.7 DSPI PUSH TX FIFO Register (DSPIx_PUSHR) .......................................................490
23.5.8 DSPI POP RX FIFO Register (DSPIx_POPR) ............................................................492
23.5.9 DSPI Transmit FIFO Registers 0–3 (DSPIx_TXFRn) .................................................493
23.6 Functional description ...................................................................................................................494
23.6.1 Modes of operation .......................................................................................................495
23.6.2 Start and stop of DSPI transfers ...................................................................................496
23.6.3 Serial peripheral interface (SPI) configuration .............................................................497
23.6.4 DSPI baud rate and clock delay generation ..................................................................500
23.6.5 Transfer formats ...........................................................................................................503
23.6.6 Continuous serial communications clock .....................................................................511
23.6.7 Interrupt requests ..........................................................................................................514
23.6.8 Power saving features ...................................................................................................515
23.7 Initialization and application information .....................................................................................516
23.7.1 How to change queues ..................................................................................................516
23.7.2 Baud rate settings .........................................................................................................516
23.7.3 Delay settings ...............................................................................................................518
23.7.4 Calculation of FIFO pointer addresses .........................................................................518
Chapter 24
Timers
24.1 Introduction ...................................................................................................................................523
24.2 Technical overview ........................................................................................................................523
24.2.1 Overview of the STM ...................................................................................................525
24.2.2 Overview of the eMIOS ...............................................................................................525
24.2.3 Overview of the PIT .....................................................................................................527
24.3 System Timer Module (STM) .......................................................................................................527
24.3.1 Introduction ..................................................................................................................527
24.3.2 External signal description ...........................................................................................528
24.3.3 Memory map and register definition ............................................................................528
24.3.4 Functional description ..................................................................................................532
24.4 Enhanced Modular IO Subsystem (eMIOS) .................................................................................532
24.4.1 Introduction ..................................................................................................................532
24.4.2 External signal description ...........................................................................................535
24.4.3 Memory map and register description ..........................................................................535
24.4.4 Functional description ..................................................................................................547
24.4.5 Initialization/Application information ..........................................................................577
24.5 Periodic Interrupt Timer (PIT) ......................................................................................................580
24.5.1 Introduction ..................................................................................................................580
24.5.2 Features .........................................................................................................................581
24.5.3 Signal description .........................................................................................................581
24.5.4 Memory map and register description ..........................................................................581
24.5.5 Functional description ..................................................................................................586
24.5.6 Initialization and application information ....................................................................587
MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 13
Chapter 25
Analog-to-Digital Converter (ADC)
25.1 Overview .......................................................................................................................................591
25.1.1 Device-specific features ...............................................................................................591
25.1.2 Device-specific implementation ...................................................................................592
25.2 Introduction ...................................................................................................................................592
25.3 Functional description ...................................................................................................................593
25.3.1 Analog channel conversion ..........................................................................................593
25.3.2 Analog clock generator and conversion timings ..........................................................597
25.3.3 ADC sampling and conversion timing .........................................................................597
25.3.4 ADC CTU (Cross Triggering Unit) ..............................................................................599
25.3.5 Presampling ..................................................................................................................600
25.3.6 Programmable analog watchdog ..................................................................................601
25.3.7 Interrupts .......................................................................................................................602
25.3.8 External decode signals delay ......................................................................................603
25.3.9 Power-down mode ........................................................................................................603
25.3.10 Auto-clock-off mode ....................................................................................................603
25.4 Register descriptions .....................................................................................................................604
25.4.1 Introduction ..................................................................................................................604
25.4.2 Control logic registers ..................................................................................................607
25.4.3 Interrupt registers ..........................................................................................................611
25.4.4 Threshold registers .......................................................................................................618
25.4.5 Presampling registers ....................................................................................................619
25.4.6 Conversion timing registers CTR[0..2] ........................................................................622
25.4.7 Mask registers ...............................................................................................................622
25.4.8 Delay registers ..............................................................................................................627
25.4.9 Data registers ................................................................................................................628
Chapter 26
Cross Triggering Unit (CTU)
26.1 Introduction ...................................................................................................................................631
26.2 Main features .................................................................................................................................631
26.3 Block diagram ...............................................................................................................................631
26.4 Memory map and register descriptions .........................................................................................631
26.4.1 Event Configuration Registers (CTU_EVTCFGRx) (x = 0...63) .................................632
26.5 Functional description ...................................................................................................................633
26.5.1 Channel value ...............................................................................................................635
Chapter 27
Flash Memory
27.1 Introduction ...................................................................................................................................639
27.2 Main features .................................................................................................................................640
27.3 Block diagram ...............................................................................................................................640
27.4 Functional description ...................................................................................................................641
27.4.1 Module structure ...........................................................................................................641
MPC5604B/C Microcontroller Reference Manual, Rev. 8
14 Freescale Semiconductor
27.4.2 Flash memory module sectorization .............................................................................642
27.4.3 TestFlash block .............................................................................................................643
27.4.4 Shadow sector ...............................................................................................................645
27.4.5 User mode operation .....................................................................................................645
27.4.6 Reset .............................................................................................................................646
27.4.7 Power-down mode ........................................................................................................647
27.4.8 Low power mode ..........................................................................................................647
27.5 Register description .......................................................................................................................648
27.5.1 CFlash register description ...........................................................................................649
27.5.2 DFlash register description ...........................................................................................680
27.6 Programming considerations .........................................................................................................703
27.6.1 Modify operation ..........................................................................................................703
27.6.2 Double word program ...................................................................................................704
27.6.3 Sector erase ...................................................................................................................706
27.7 Platform flash memory controller .................................................................................................714
27.7.1 Introduction ..................................................................................................................714
27.7.2 Memory map and register description ..........................................................................717
27.8 Functional description ...................................................................................................................726
27.8.1 Access protections ........................................................................................................727
27.8.2 Read cycles – Buffer miss ............................................................................................727
27.8.3 Read cycles – Buffer hit ...............................................................................................727
27.8.4 Write cycles ..................................................................................................................727
27.8.5 Error termination ..........................................................................................................727
27.8.6 Access pipelining ..........................................................................................................728
27.8.7 Flash error response operation ......................................................................................728
27.8.8 Bank0 page read buffers and prefetch operation ..........................................................728
27.8.9 Bank1 Temporary Holding Register .............................................................................730
27.8.10 Read-while-write functionality .....................................................................................731
27.8.11 Wait-state emulation .....................................................................................................732
Chapter 28
Static RAM (SRAM)
28.1 Introduction ...................................................................................................................................735
28.2 Low power configuration ..............................................................................................................735
28.3 Register memory map ...................................................................................................................735
28.4 SRAM ECC mechanism ................................................................................................................735
28.4.1 Access timing ...............................................................................................................736
28.4.2 Reset effects on SRAM accesses ..................................................................................737
28.5 Functional description ...................................................................................................................737
28.6 Initialization and application information .....................................................................................737
Chapter 29
Register Protection
29.1 Introduction ...................................................................................................................................741
29.2 Features .........................................................................................................................................741
MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 15
29.3 Modes of operation ........................................................................................................................742
29.4 External signal description ............................................................................................................742
29.5 Memory map and register description ...........................................................................................742
29.5.1 Memory map ................................................................................................................743
29.5.2 Register description ......................................................................................................744
29.6 Functional description ...................................................................................................................746
29.6.1 General .........................................................................................................................746
29.6.2 Change lock settings .....................................................................................................746
29.6.3 Access errors ................................................................................................................750
29.7 Reset ..............................................................................................................................................750
29.8 Protected registers .........................................................................................................................750
Chapter 30
Software Watchdog Timer (SWT)
30.1 Overview .......................................................................................................................................755
30.2 Features .........................................................................................................................................755
30.3 Modes of operation ........................................................................................................................755
30.4 External signal description ............................................................................................................756
30.5 Memory map and register description ...........................................................................................756
30.5.1 Memory map ................................................................................................................756
30.5.2 Register description ......................................................................................................757
30.6 Functional description ...................................................................................................................761
Chapter 31
Error Correction Status Module (ECSM)
31.1 Introduction ...................................................................................................................................763
31.2 Overview .......................................................................................................................................763
31.3 Features .........................................................................................................................................763
31.4 Memory map and register description ...........................................................................................763
31.4.1 Memory map ................................................................................................................763
31.4.2 Register description ......................................................................................................764
31.4.3 Register protection ........................................................................................................783
Chapter 32
IEEE 1149.1 Test Access Port Controller (JTAGC)
32.1 Introduction ...................................................................................................................................787
32.2 Block diagram ...............................................................................................................................787
32.3 Overview .......................................................................................................................................787
32.4 Features .........................................................................................................................................788
32.5 Modes of operation ........................................................................................................................788
32.5.1 Reset .............................................................................................................................788
32.5.2 IEEE 1149.1-2001 defined test modes .........................................................................788
32.6 External signal description ............................................................................................................789
32.7 Memory map and register description ...........................................................................................790
32.7.1 Instruction Register ......................................................................................................790
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