OV13850传感器规格书：OmniVision技术详细解析

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"OV13850-G04A是OmniVision公司的一款传感器规格文档，详细介绍了该传感器的特性、功能以及与MIPI Camera Command Set (CCS) V1.1的兼容性。该文档可能包含了关于图像传感器的技术参数、接口规范、性能指标等内容。" OV13850是OmniVision Technologies生产的一款高性能CMOS图像传感器，常用于智能手机、安防监控、工业应用等领域。这款传感器提供了高分辨率的图像捕捉能力，以满足各种应用场景对图像质量的需求。文档中的"Specification for CCS Version 1.1"部分提到了它与MIPI Alliance的Camera Command Set (CCS)的兼容性，这意味着OV13850支持MIPI CSI-2接口，这是一种高速、低功耗的数据传输标准，广泛应用于移动设备和摄像头模块。 MIPI Camera Command Set (CCS) 是MIPI Alliance制定的一套标准，用于定义摄像头模组与主机处理器之间的通信协议。CCS V1.1版本提供了更完善的命令集，用于控制摄像头的配置、图像捕获、流控制等操作。通过遵循这一标准，OV13850能与其他遵循MIPI协议的设备无缝集成，确保稳定且高效的图像数据传输。文档中提到的"2 December 2019"和"Public Release Edition"表明这是2019年12月公开发布的版本，意味着它是当时最新的技术规格。此外，文档还包含了免责声明，指出提供的信息可能存在瑕疵，不提供任何明示或暗示的保修，包括但不限于适销性、特定用途适用性、准确性、完整性的保修，同时也不存在权利、安静享受、无瑕疵拥有、符合描述或非侵权的保修。 OV13850的具体规格可能包括像素尺寸、感光面积、最大分辨率、帧率、动态范围、信噪比、色彩深度等。在实际应用中，这些参数会影响传感器的成像质量和性能。例如，高分辨率和高帧率适用于高速运动场景，而大像素尺寸则可以提高图像的感光性能，降低噪点。此外，传感器可能还具备多种曝光模式、白平衡设置、数字信号处理功能等，以适应不同光照环境和拍摄需求。 "Sensor OV13850-G04A OmniVision Specification (V1.1).pdf"这份文档详细阐述了OV13850传感器的技术规格，包括其与MIPI标准的兼容性，对于理解该传感器的性能特点、设计集成以及优化应用具有重要参考价值。

Specification for CCS Version 1.1

02-Dec-2019

Public Release Edition

Table 65 Tagged Data Format Tag Code Summary ...................................................................... 102

Table 66 Example of Addressable Pixel Array Size ..................................................................... 107

Table 67 Pixel Array Address Registers ....................................................................................... 109

Table 68 Pixel Array Address Capability Registers ...................................................................... 110

Table 69 Output Image Size Registers ......................................................................................... 113

Table 70 Output Size Limits ......................................................................................................... 114

Table 71 Image Orientation Register ............................................................................................ 116

Table 72 Contents of Image Orientation Register ........................................................................ 116

Table 73 Pixel Order Register (Read Only Dynamic) .................................................................. 117

Table 74 Color Pixel Order Code ................................................................................................. 117

Table 75 X and Y-Address Increment Registers ........................................................................... 118

Table 76 X and Y-Address Increment Parameter Limits and Sub-sampling Capability

for Bayer Pixel Readout .............................................................................................. 119

Table 77 Pixel Readout Capability Register ................................................................................. 120

Table 78 Monochrome Readout Capability, Sub-sampling Limits, and Control Registers .......... 121

Table 79 Binning Capability Register .......................................................................................... 126

Table 80 X and Y-Address Increment Parameter Limits for binning_capability = 2 ................... 127

Table 81 Binning Mode Register .................................................................................................. 128

Table 82 Binning Control Registers ............................................................................................. 128

Table 83 Video Timing Registers ................................................................................................. 132

Table 84 Frame Timing Parameter Limits .................................................................................... 134

Table 85 Frame Blanking Register ............................................................................................... 134

Table 86 Frame Timing Parameter Limits for Binning mode....................................................... 135

Table 87 PLL Control and Capability Registers ........................................................................... 137

Table 88 Clocking Example (Assuming op_bits_per_lane = 0) ................................................... 148

Table 89 Clocking Example (Assuming op_bit_per_lane = 0) .................................................... 154

Table 90 Clock Division and PLL Multiplier Registers for Simple One-PLL System ................. 157

Table 91 Clock Division and PLL Multiplier Registers for One-PLL System ............................. 157

Table 92 Clock Division and PLL Multiplier Registers for Two-PLL System ............................. 158

Table 93 Video Timing Pixel Clock Divider Register .................................................................. 159

Table 94 Video Timing System Clock Divider Register .............................................................. 159

Table 95 Pre-PLL Clock Divider Registers .................................................................................. 160

Table 96 PLL Multiplier Registers ............................................................................................... 161

Version 1.1 Specification for CCS

02-Dec-2019

Public Release Edition

Table 97 Output Pixel Clock Divider Register ............................................................................. 161

Table 98 Output System Clock Divider Register ......................................................................... 161

Table 99 Clock Capability Type Register ..................................................................................... 162

Table 100 Pre PLL and PLL Clock Set-Up Capability Registers ................................................. 162

Table 101 Video Timing Clock Set-Up Capability Registers ....................................................... 164

Table 102 Output Clock Set-Up Capability Registers .................................................................. 165

Table 103 D-PHY Per-Lane Bitrate Limit Registers .................................................................... 166

Table 104 C-PHY Per-Lane Symbol Rate Limit Registers .......................................................... 167

Table 105 Integration Time Control Parameters ........................................................................... 171

Table 106 Analog Gain Capability Parameters ............................................................................. 173

Table 107 Gain Mode Register ..................................................................................................... 173

Table 108 Analog Gain Control Parameters ................................................................................. 174

Table 109 Analog Gain Coding/Decoding Constants ................................................................... 175

Table 110 Gain Parameter Limits ................................................................................................. 175

Table 111 Alternate Analog Gain Control Parameters .................................................................. 176

Table 112 Alternate Gain Parameter Limits ................................................................................. 176

Table 113 Digital Gain Control Parameters .................................................................................. 178

Table 114 Digital Gain Capability ................................................................................................ 178

Table 115 Digital Gain Limit & Precision Parameters ................................................................. 178

Table 116 Grouped Change Control Parameter ............................................................................ 179

Table 117 Mask Corrupted Frames Register ................................................................................ 180

Table 118 Gain Delay Type Register ............................................................................................ 181

Table 119 Integration Time Parameter Limits .............................................................................. 182

Table 120 Timing Mode Capability Registers .............................................................................. 184

Table 121 Timing Mode Control Registers .................................................................................. 184

Table 122 Automatic Frame Length Control Registers ................................................................ 185

Table 123 Manual Readout Control Registers .............................................................................. 187

Table 124 Bracketing LUT Capability Registers .......................................................................... 190

Table 125 Example 1 LUT Content .............................................................................................. 191

Table 126 Example 2 LUT Content .............................................................................................. 192

Table 127 Possible LUT Entry Types ........................................................................................... 192

Table 128 Bracketing Configuration Registers ............................................................................ 193

Table 129 HDR_internal_bit_depth Value as a Function of Exposure Ratio ............................... 196

Specification for CCS Version 1.1

02-Dec-2019

Public Release Edition

Table 130 HDR Capability Registers ........................................................................................... 199

Table 131 HDR Control Registers ................................................................................................ 200

Table 132 Main Full Frame Test Pattern Control Parameter ........................................................ 203

Table 133 Test Mode Capability ................................................................................................... 203

Table 134 Test Data Color Parameters ......................................................................................... 204

Table 135 100% Color Bar Values ............................................................................................... 205

Table 136 Test Pattern Capability Registers ................................................................................. 206

Table 137 Example of Fade to Grey Values ................................................................................. 210

Table 138 Fade to Grey Control Registers ................................................................................... 210

Table 139 100% Color Tile Values ............................................................................................... 213

Table 140 PN9 Capability Registers ............................................................................................. 216

Table 141 Image Scaling Capability Register .............................................................................. 217

Table 142 Digital Crop Capability Register ................................................................................. 217

Table 143 Digital Crop Control Register ...................................................................................... 218

Table 144 Image Scaling Registers .............................................................................................. 221

Table 145 Image Scaling Capability Registers ............................................................................. 221

Table 146 FIFO Control Registers................................................................................................ 222

Table 147 Compression Mode Register........................................................................................ 223

Table 148 Compression Capability Register ................................................................................ 223

Table 149 Data Transfer Interface Capability Registers ............................................................... 225

Table 150 Data Transfer Interface 1 Registers ............................................................................. 226

Table 151 Sensor Processing Capabilities .................................................................................... 230

Table 152 Shading Correction Control ......................................................................................... 231

Table 153 Luminance Correction Control .................................................................................... 231

Table 154 Green Imbalance Correction Control ........................................................................... 231

Table 155 Mapped Defect Correction Control ............................................................................. 232

Table 156 Dynamic Couplet Correction Control .......................................................................... 232

Table 157 Single Pixel Correction Control ................................................................................... 232

Table 158 Combined Defect Correction Control .......................................................................... 233

Table 159 Dynamic Triplet Defect Correction Control ................................................................ 233

Table 160 Noise Filter Control ..................................................................................................... 234

Table 161 Module Specific Correction Control ........................................................................... 234

Table 162 Color Temperature Feedback Capability ..................................................................... 235

Version 1.1 Specification for CCS

02-Dec-2019

Public Release Edition

Table 163 Color Temperature Feedback Locations ...................................................................... 235

Table 164 Optical Black Readout Control .................................................................................... 237

Table 165 Optical Black Readout Capability ............................................................................... 237

Table 166 Flash Strobe Capability Register ................................................................................. 241

Table 167 Flash Strobe Adjustment Register ............................................................................... 241

Table 168 Achievable Flash Strobe Range ................................................................................... 242

Table 169 Strobe Config Registers ............................................................................................... 242

Table 170 Flash Strobe Control Register ...................................................................................... 243

Table 171 Flash Status Register ................................................................................................... 243

Table 172 SA_strobe Capability Register .................................................................................... 245

Table 173 Special Actuator Strobe Config Register ..................................................................... 246

Table 174 Special Actuator Strobe Status Register ...................................................................... 246

Table 175 PDAF Registers ........................................................................................................... 248

Table 176 Temperature Sensor Registers ..................................................................................... 254

Table 177 Temperature Sensor Output Format ............................................................................. 255

Table 178 CCI Address Control ................................................................................................... 258

Table 179 CCI Register Groupings .............................................................................................. 261

Table 180 Valid Register Formats ................................................................................................ 266

Table 181 General Status Registers .............................................................................................. 267

Table 182 Frame Format Description Registers ........................................................................... 269

Table 183 Analog Gain Description Registers ............................................................................. 271

Table 184 Data Format Description Registers .............................................................................. 273

Table 185 General Set-Up Registers ............................................................................................ 274

Table 186 Output Set-Up Registers .............................................................................................. 275

Table 187 Gain Set-Up Registers ................................................................................................. 276

Table 188 ADC Set-up Registers .................................................................................................. 276

Table 189 Generic Control Registers............................................................................................ 276

Table 190 GPIO Set-Up Registers ................................................................................................ 276

Table 191 Reference Clock Frequency Registers ......................................................................... 276

Table 192 Temperature Sensor Registers ..................................................................................... 277

Table 193 Integration Time Registers ........................................................................................... 277

Table 194 Analog Gain Registers ................................................................................................. 277

Table 195 Digital Gain Registers ................................................................................................. 277

Specification for CCS Version 1.1

02-Dec-2019

Public Release Edition

Table 196 HDR Control Registers ................................................................................................ 278

Table 197 Clock Set-Up Registers................................................................................................ 279

Table 198 Frame Timing Registers ............................................................................................... 280

Table 199 Image Size Registers.................................................................................................... 280

Table 200 Timing Mode Registers................................................................................................ 281

Table 201 Sub-Sampling Registers............................................................................................... 281

Table 202 Monochrome Readout Registers .................................................................................. 281

Table 203 Image Scaling Registers .............................................................................................. 282

Table 204 Image Compression Registers ..................................................................................... 283

Table 205 Test Pattern Registers................................................................................................... 283

Table 206 PHY Configuration Registers ...................................................................................... 284

Table 207 CSI-2 Requested Link Rate Registers ......................................................................... 285

Table 208 Equalization Control Registers .................................................................................... 285

Table 209 D-PHY Preamble Control Registers ............................................................................ 285

Table 210 D-PHY Spread Spectrum Control Register ................................................................. 285

Table 211 Manual LP Control Register ........................................................................................ 285

Table 212 Additional PHY Configuration Registers .................................................................... 286

Table 213 D-PHY 1.2 Related Configuration Registers ............................................................... 287

Table 214 C-PHY Manual Control Registers ............................................................................... 288

Table 215 ALPS Feature Control Registers .................................................................................. 289

Table 216 LRTE Feature Control Registers ................................................................................. 289

Table 217 Data Scrambling Feature Control Registers ................................................................ 290

Table 218 USL Control Registers ................................................................................................. 292

Table 219 Binning Configuration Registers ................................................................................. 293

Table 220 Data Transfer Interface Configuration Registers ......................................................... 293

Table 221 Sensor Correction Configuration Registers ................................................................. 294

Table 222 Optical Black Pixel Readout Registers ........................................................................ 295

Table 223 Color Temperature Feedback Registers ....................................................................... 295

Table 224 CFA Conversion Registers ........................................................................................... 295

Table 225 Flash and SA Strobe Configuration ............................................................................. 296

Table 226 PDAF Control Registers .............................................................................................. 297

Table 227 Bracketing Interface Configuration Registers ............................................................. 298

Table 228 Integration Time Capability Registers ......................................................................... 299

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