ARM Cortex-M4 LPC4330微控制器用户手册概览

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ARM-M4_LPC4330是一款基于ARM Cortex-M4内核的NXP LPC4330系列微控制器，这款英文用户手册（UM10503）提供了详细的规格、功能和接口描述，适用于LPC4300系列中的多个型号，如LPC4350、LPC4330、LPC4320和LPC4310等。该系列微控制器集成了多种功能模块，包括但不限于： 1. **ARM Cortex-M4/M0双核处理器**：强调了它拥有Cortex-M4和Cortex-M0两种核心架构，这使得它具备高性能计算能力和低功耗特性，适合于对能源效率有较高要求的应用。 2. **SPIFI** (Serial Peripheral Interface Flash Interface)：提供了串行闪存接口，用于扩展存储容量和简化外部设备连接。 3. **SCT (System Control Timer)**：一个高度灵活的定时器模块，用于实现精确的时间管理、中断触发等功能。 4. **USB（Universal Serial Bus）支持**：文档提到了USB CDC（Communication Device Class）接口，这表明LPC4330支持作为USB设备，可连接到电脑或其他USB设备进行数据传输。 5. **以太网**：内置以太网控制器，使得微控制器能够通过网络通信，适用于需要高速数据传输或远程控制的应用。 6. **电源优化**：文档更新了关于USB电源优化的内容，可能涉及如何有效管理和利用电源，以提高系统的整体能效。 7. **修订历史**：手册的版本1.3包含了对USB CDC接口API的更新，新增了USB 1模块的控制功能，并对USB电源优化部分进行了改进。通过阅读这份手册，开发人员可以深入了解LPC4330的硬件特性和编程接口，以便将其集成到自己的项目中。同时，由于强调了学习共享的精神，对于那些希望深入研究或者寻求帮助的读者，这是一份宝贵的资源。

User manual Rev. 1.3 — 6 July 2012 16 of 1269

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Chapter 2: LPC43xx ARM Cortex-M0 co-processor and Inter- Process

2.5.3 Example

Assume a certain task with ID 0x1234 should be executed by the ARM Cortex-M0. For

example, read data from a register level interface controlled by the ARM Cortex-M0. Text

in bold indicates a register.

The registers can either be located in the ARM Cortex-M0 SRAM, for more deterministic

access times, or in shared SRAM. If the ARM Cortex-M0 SRAM is used, then the register

data needs to be copied at initialization time. This copying takes time. The ARM

Cortex-M4 can poll a status register to determine when the transfer has finished.

The ARM Cortex-M4 initializes the command and message queues by loading the start-

and end addresses and write and read pointers.

Then the ARM Cortex-M4 loads the register values in a reserved area in common SRAM

memory. An alternative approach is that the ARM Cortex-M4 writes register per register,

however this requires more communication overhead than loading all data in one go.

Once all data has been set up, the ARM Cortex-M0 task can be started.

Table 7. Message list

Message Bit mask Description

MSG_SRV_ID 0xTTTT.SS00 ARM Cortex-M0 request servicing for the task

with ID = 0xTTTT. The service type is coded in

bytes SS. The meaning of SS is proprietary per

task. SS=0x00 means the task has finished.

MSG_RD_ID 0xTTTT.PPP1, VALUE ARM Cortex-M0 responds with VALUE to a read

of WORD with argument ID=0xPPP* from the

task with ID = 0xTTTT.

MSG_RD_STS_ID 0xTTTT.PPPR ARM Cortex-M0 response to a read of WORD

with argument ID=0xPPP* from the task with ID

= 0xTTTT fails. Cause of the failure is coded in

R; R = 2...4

2 = invalid argument

3 = reserved

4 = reserved

MSG_WR_STS_ID 0xTTTT.PPPW ARM Cortex-M0 response to a write with

argument ID=0xPPP* from the task with ID =

0xTTTT. Response is coded in W; W = 5...7

5 = write was successful

6 = write failed

7 = reserved

Table 8. Command responses

Command Possible responses Description

CMD_RD_ID MSG_RD_ID, VALUE read acknowledged

MSG_RD_STS_ID read failed

CMD_WR, WORD MSG_WR_STS_ID write is acknowledged as a success or failure

User manual Rev. 1.3 — 6 July 2012 19 of 1269

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Chapter 3: LPC43xx Memory mapping

[1] To configure SRAM memory use for AHB or ETB, see Table 49.

3.3.2 Bit banding

Bit-banding offers efficient bit accesses. Bits in the bit-band region (0x2000 0000 to

0x2010 0000 and 0x4000 0000 to 0x4010 0000) can be accessed in the so-called alias

region at 0x2200 0000 and 0x4200 0000. Reads return the respective bit from the

bit-band region. Writes perform an atomic read-modify-write on the respective bit of the

bit-band region. For details, see the ARM Cortex-M4 technical reference manual.

Remark: Bit banding can not be used with the MAC_RWAKE_FRFLT register (see

Section 26.6.10

Remark: Although the EEPROM is mapped in a bit-banding capable region, attempts to

write access the EEPROM in the bit-banding aliased memory space will not result in a bit

write

3.3.3 On-chip flash

The available flash configuration for the LPC435x/3x/2x/1x is shown in Table 11. An

integrated flash accelerator maximizes performance for use with the two fast AHB buses.

The flash memory interface includes an intelligent buffering scheme. It can be beneficial

to locate code and static data over the two flash memories to enable parallel code and

data access or to avoid that interrupts corrupt buffer content. The buffers are aligned on

32-byte boundaries.

LPC4310 96 kB 40 kB 16 kB - 16 kB Figure 4

LPC4357 32 kB 40 kB 32 kB 16 kB 16 kB Figure 6

LPC4353 32 kB 40 kB 32 kB 16 kB 16 kB Figure 6

LPC4337 32 kB 40 kB 32 kB 16 kB 16 kB Figure 6

LPC4333 32 kB 40 kB 32 kB 16 kB 16 kB Figure 6

Table 10. LPC43xx SRAM configuration

Part Local SRAM Local SRAM AHB SRAM AHB SRAM AHB

SRAM/

ETB

SRAM

[1]

0x1000 0000

0x1008 0000

0x2000 0000

0x2000 8000

0x2000 C000

Table 11. LPC435x/3x/2x/1x Flash configuration

Part Flash bank A

256 kB

Flash bank A

128 kB

Flash bank A

128 kB

Flash bank B

256 kB

Flash bank B

128 kB

Flash bank B

128 kB

0x1A00 0000 0x1A04 000 0x1A0 6000 0x1B00 0000 0x1B04 000 0x1B0 6000

LPC4357 yes yes yes yes yes yes

User manual Rev. 1.3 — 6 July 2012 20 of 1269

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Chapter 3: LPC43xx Memory mapping

3.3.4 On-chip EEPROM

The LPC435x/3x/2x/1x parts with flash also include a 16 kB EEPROM. The EEPROM is

divided into 128 pages. The last EEPROM page is protected.

3.3.5 Memory retention in the Power-down modes

In Deep-sleep mode, all SRAM content is retained. At wake-up the system can restart

immediately.

In Power-down mode, only the top 8 kB of the SRAM block starting at 0x1008 0000 is

retained - that is 8 kB of SRAM located at 0x1009 0000. All other SRAM content is lost.

Common practice is to store the stack and other variables that need to be retained in this

8 kB memory space as well as code to restart the rest of the system.

In Deep power-down mode, no SRAM content is retained. Variables that need to be

retained in deep power down can be stored in the 256-byte register file located in the RTC

domain at 0x4004 1000.

3.3.6 Memory Protection Unit (MPU)

The MPU is a integral part of the ARM Cortex-M4 for memory protection and supported by

all LPC43xx parts. The processor supports the standard ARMv7 Protected Memory

System Architecture model. The MPU provides full support for:

• protection regions

• overlapping protection regions, with ascending region priority (7 = highest priority, 0 =

lowest priority)

• access permissions

• exporting memory attributes to the system

MPU mismatches and permission violations invoke the programmable-priority

MemManage fault handler. See the ARMv7-M Architecture Reference Manual for more

information.

The access permission bits, TEX, C, B, AP, and XN, of the Region Access Control

area of memory without the required permissions, a permission fault is raised. For more

information, see the ARMv7-M Architecture Reference Manual.

The MPU is used to enforce privilege rules, to separate processes, and to enforce access

rules. For details on how to use the MPU and for the register description refer to the ARM

Cortex-M4 Technical Reference Manual.

LPC4353 yes no no yes no no

LPC4337 yes yes yes yes yes yes

LPC4333 yes no no yes no no

Table 11. LPC435x/3x/2x/1x Flash configuration

Part Flash bank A

256 kB

Flash bank A

128 kB

Flash bank A

128 kB

Flash bank B

256 kB

Flash bank B

128 kB

Flash bank B

128 kB

0x1A00 0000 0x1A04 000 0x1A0 6000 0x1B00 0000 0x1B04 000 0x1B0 6000

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