22 Synopsys, Inc.
SolvNet
DesignWare.com
2.21a
October 2016
Product Overview DesignWare DW_ahb_dmac Databook
■
Memory – Source or destination that is always “ready” for a DMA transfer and does not require a
handshaking interface to interact with the DW_ahb_dmac. A peripheral should be assigned as
memory only if it does not insert more than 16 wait states. If more than 16 wait states are required,
then the peripheral should use a handshaking interface—the default if the peripheral is not
programmed to be memory—in order to signal when the peripheral is ready to accept or supply data.
A memory peripheral can also generate SPLIT/RETRY responses.
■
Channel – Read/write data path between a source peripheral on one configured AHB layer and a
destination peripheral on the same or different AHB layer that occurs through the channel FIFO. If
the source peripheral is not memory, then a source handshaking interface is assigned to the channel.
If the destination peripheral is not memory, then a destination handshaking interface is assigned to
the channel. Source and destination handshaking interfaces can be assigned dynamically by
programming the channel registers.
■
Master interface – DW_ahb_dmac is a master on the AHB bus, reading data from the source and
writing it to the destination over the AHB bus. It is possible to have up to four master interfaces,
which means that up to four independent source and destination channels can operate
simultaneously. Each channel has to arbitrate for the master interface. You need to have more than
one master interface if the source and destination peripherals reside on different AHB layers.
■
Slave interface – The AHB interface over which the DW_ahb_dmac is programmed. The slave
interface in practice can be on the same layer as any of the master interfaces, or it can be on a separate
layer.
■
Handshaking interface – A set of signals or software registers that conform to a protocol and
handshake between the DW_ahb_dmac and source or destination peripheral in order to control
transferring a single or burst transaction between them. This interface is used to request,
acknowledge, and control a DW_ahb_dmac transaction. A channel can receive a request through one
of three types of handshaking interface: hardware, software, or peripheral interrupt.
❑
Hardware handshaking interface – Uses hardware signals to control transferring a single or
burst transaction between the DW_ahb_dmac and the source or destination peripheral. For more
information about this interface, refer to “Hardware Handshaking – Peripheral Is Not Flow
Controller” on page 54 and “Hardware Handshaking – Peripheral Is Flow Controller” on
page 63.
❑
Software handshaking interface– Uses software registers to control transferring a single or burst
transaction between the DW_ahb_dmac and the source or destination peripheral. No special
DW_ahb_dmac handshaking signals are needed on the I/O of the peripheral. This mode is useful
for interfacing an existing peripheral to the DW_ahb_dmac without modifying it. For more
information about this interface, refer to “Flow Control Configurations” on page 102.
❑
Peripheral interrupt handshaking interface – Simple use of the hardware handshaking interface.
In this mode, the interrupt line from the peripheral is tied to the dma_req input of the hardware
handshaking interface; other interface signals are ignored. For more information about this
interface, refer to “Peripheral Interrupt Request Interface” on page 101.
■
Flow controller – Device (either the DW_ahb_dmac, or source/destination peripheral) that
determines the length of a DMA block transfer and terminates it.
❑
If you know the length of a block before enabling the channel, then you should program the
DW_ahb_dmac as the flow controller.
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