IEEE 802.3cd: 50G/100G/200G Ethernet Amendment for Media Access and Physical Layers

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IEEE 802.3cd-2018 是一项针对以太网（Ethernet）标准的修正案，它专注于50Gbps、100Gbps和200Gbps高速数据传输，以适应现代数据中心和云计算环境对带宽的需求增长。这份标准由 LAN/MAN 标准委员会（Local Area Network / Metropolitan Area Network Standards Committee）赞助，隶属于 IEEE 计算机协会（IEEE Computer Society），并基于先前的 IEEE 802.3 标准（2018年修订版）进行扩展，如 IEEE 802.3cb 和 IEEE 802.3bt。该标准关注的核心内容包括以下几个方面： 1. **媒体访问控制（Media Access Control, MAC）参数**：在802.3cd中，MAC层的设计目标是支持这些高带宽的传输，确保数据在50Gbps、100Gbps和200Gbps速率下能够高效地接入网络，同时保持低延迟和高效率。MAC协议可能涉及新的帧结构、多速率支持以及流量管理策略，以优化数据包的发送和接收。 2. **物理层（Physical Layer）设计**：随着数据速率的提升，物理层也需要相应的技术升级。这可能涉及到采用新型调制技术，如PAM4（四电平脉冲幅度调制），以在单个信道（lane）上实现更高的数据密度。PAM4技术通过使用四个电压水平来编码数据比特，相较于传统的PAM4双电平（如PAM2或PAM4），可以更有效地利用信号带宽，提高传输效率。 3. **管理和维护参数**：标准还定义了管理和维护功能，确保这些高速以太网系统的稳定运行和故障检测。这包括错误检测和纠正机制、电源管理和温度监控等，以保证系统的可靠性和安全性。 4. **标准化与授权**：IEEE 802.3cd-2018 标准获得了IEEE-SA 标准董事会的批准，并对用户使用设有限制，只能在下载自IEEE Explore时遵守特定的使用条款和条件。 5. **时间戳信息**：文档提到的"Approved 5 December 2018"表明该标准是在2018年12月5日获得正式批准的，而下载日期为2021年12月18日，显示其仍具有一定的时效性，可能需要跟踪后续的更新或兼容性要求。 IEEE 802.3cd-2018是当前高速以太网技术的重要组成部分，它为数据中心和云计算环境提供了关键的连接标准，促进了数据传输性能的显著提升。随着技术的不断发展，该标准将不断演进，以满足未来更高带宽和更低延迟的需求。

45.2.3.15.4 BASE-R and MultiGBASE-T PCS high BER (3.32.1) ..................................... 75

45.2.3.15.5 BASE-R and MultiGBASE-T PCS block lock (3.32.0) .................................... 75

45.2.3.16 BASE-R and MultiGBASE-T PCS status 2 register (Register 3.33) ......................... 75

45.2.3.16.1 Latched block lock (3.33.15) ............................................................................. 75

45.2.3.16.2 Latched high BER (3.33.14) .............................................................................. 75

45.2.3.16.3 BER (3.33.13:8)................................................................................................. 76

45.2.3.16.4 Errored blocks (3.33.7:0) ................................................................................... 76

45.2.3.19 BASE-R PCS test-pattern control register (Register 3.42)......................................... 76

45.2.7 Auto-Negotiation registers..................................................................................................... 76

45.2.7.12 Backplane Ethernet, BASE-R copper status (Register 7.48)...................................... 76

45.2.7.12.3 Negotiated Port Type (7.48.1, 7.48.2, 7.48.3, 7.48.5, 7.48.6, 7.48.8, 7.48.9,

7.48.10, 7.48.11, 7.48.12, 7.48.13, 7.48.14, 7.48.15, 7.49.0, 7.49.1,

7.49.2) ............................................................................................................. 76

45.2.7.12a Backplane Ethernet, BASE-R copper status 2 (Register 7.49) ................................. 77

45.2.7.12a.1 Negotiated Port Type ....................................................................................... 77

69. Introduction to Ethernet operation over electrical backplanes ............................................................... 78

69.1 Overview......................................................................................................................................... 78

69.1.1 Scope...................................................................................................................................... 78

69.1.2 Relationship of Backplane Ethernet to the ISO OSI reference model................................... 78

69.2 Summary of Backplane Ethernet Sublayers ................................................................................... 80

69.2.1 Reconciliation sublayer and media independent interfaces................................................... 80

69.2.3 Physical Layer signaling systems .......................................................................................... 80

69.3 Delay constraints............................................................................................................................. 82

69.5 Protocol implementation conformance statement (PICS) proforma............................................... 82

73. Auto-Negotiation for backplane and copper cable assembly ................................................................. 83

73.2 Relationship to the ISO/IEC Open Systems Interconnection (OSI) reference model .................... 83

73.5 DME transmission .......................................................................................................................... 83

73.5.1 DME electrical specifications................................................................................................ 83

73.6 Link codeword encoding ................................................................................................................ 84

73.6.4 Technology Ability Field....................................................................................................... 84

73.7 Receive function requirements ....................................................................................................... 85

73.7.6 Priority Resolution function................................................................................................... 85

73.10 State diagrams and variable definitions ........................................................................................ 86

73.10.1 State diagram variables........................................................................................................ 86

73.10.2 State diagram timers ............................................................................................................ 87

78. Energy-Efficient Ethernet (EEE) ............................................................................................................ 88

78.1 Overview......................................................................................................................................... 88

78.1.4 PHY types optionally supporting EEE .................................................................................. 88

78.5 Communication link access latency................................................................................................ 89

80. Introduction to 40 Gb/s and 100 Gb/s networks ..................................................................................... 90

80.1 Overview......................................................................................................................................... 90

80.1.3 Relationship of 40 Gigabit and 100 Gigabit Ethernet to the ISO OSI reference model........ 90

80.1.4 Nomenclature......................................................................................................................... 91

80.1.5 Physical Layer signaling systems .......................................................................................... 92

80.2 Summary of 40 Gigabit and 100 Gigabit Ethernet sublayers ......................................................... 93

80.2.2 Physical Coding Sublayer (PCS) ........................................................................................... 93

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80.2.3 Forward Error Correction (FEC) sublayers ........................................................................... 93

80.2.4 Physical Medium Attachment (PMA) sublayer..................................................................... 94

80.2.5 Physical Medium Dependent (PMD) sublayer ...................................................................... 94

80.2.6 Auto-Negotiation ................................................................................................................... 94

80.4 Delay constraints............................................................................................................................. 95

80.5 Skew constraints ............................................................................................................................. 96

80.7 Protocol implementation conformance statement (PICS) proforma............................................... 99

82. Physical Coding Sublayer (PCS) for 64B/66B, type 40GBASE-R and 100GBASE-R ....................... 100

82.6 Auto-Negotiation .......................................................................................................................... 100

82.7 Protocol implementation conformance statement (PICS) proforma for Clause 82, Physical

Coding Sublayer (PCS) for 64B/66B, type 40GBASE-R and 100GBASE-R.......................... 100

82.7.4 PICS proforma tables for PCS, type 40GBASE-R and 100GBASE-R ............................... 100

82.7.4.11 Auto-Negotiation for Backplane Ethernet functions ................................................ 100

90. Ethernet support for time synchronization protocols............................................................................ 101

90.1 Introduction................................................................................................................................... 101

91. Reed-Solomon Forward Error Correction (RS-FEC) sublayer for 100GBASE-R PHYs .................... 102

91.3 PMA compatibility ....................................................................................................................... 102

91.5 Functions within the RS-FEC sublayer ........................................................................................ 102

91.5.2 Transmit function................................................................................................................. 102

91.5.2.6 Alignment marker mapping and insertion .................................................................. 102

91.5.2.7 Reed-Solomon encoder............................................................................................... 102

91.5.3 Receive function .................................................................................................................. 103

91.5.3.3 Reed-Solomon decoder............................................................................................... 103

91.5.3.3.1 FEC Degraded SER (optional) .......................................................................... 103

91.6 RS-FEC MDIO function mapping................................................................................................ 104

91.6.2a four_lane_pmd ................................................................................................................... 104

91.6.2b FEC_degraded_SER_enable.............................................................................................. 104

91.6.2c FEC_degraded_SER_activate_threshold ........................................................................... 105

91.6.2d FEC_degraded_SER_deactivate_threshold ....................................................................... 105

91.6.2e FEC_degraded_SER_interval ............................................................................................ 105

91.6.5a FEC_degraded_SER_ability .............................................................................................. 105

91.6.5b FEC_degraded_SER .......................................................................................................... 105

91.7 Protocol implementation conformance statement (PICS) proforma for Clause 91, Reed-

Solomon Forward Error Correction (RS-FEC) sublayer for 100GBASE-R PHYs.................. 105

91.7.3 Major capabilities/options.................................................................................................... 105

91.7.4 PICS proforma tables for Reed-Solomon Forward Error Correction (RS-FEC) sublayer

for 100GBASE-R PHYs ................................................................................................... 106

91.7.4.1 Transmit function........................................................................................................ 106

91.7.4.2 Receive function ......................................................................................................... 106

116. Introduction to 200 Gb/s and 400 Gb/s networks ............................................................................... 108

116.1 Overview..................................................................................................................................... 108

116.1.2 Relationship of 200 Gigabit and 400 Gigabit Ethernet to the ISO OSI reference

model ................................................................................................................................ 108

116.1.3 Nomenclature..................................................................................................................... 108

116.1.4 Physical Layer signaling systems ...................................................................................... 108

116.2 Summary of 200 Gigabit and 400 Gigabit Ethernet sublayers ................................................... 110

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116.2.5 Physical Medium Dependent (PMD) sublayer .................................................................. 110

116.4 Delay constraints......................................................................................................................... 110

119. Physical Coding Sublayer (PCS) for 64B/66B, type 200GBASE-R and 400GBASE-R ................... 111

119.5a Auto-Negotiation ...................................................................................................................... 111

119.6 Protocol implementation conformance statement (PICS) proforma for Clause 119, Physical

Coding Sublayer (PCS) for 64B/66B, type 200GBASE-R and 400GBASE-R........................ 111

119.6.4 PICS proforma tables for Physical Coding Sublayer (PCS) 64B/66B, type

200GBASE-R and 400GBASE-R .................................................................................... 111

119.6.4.12 Auto-Negotiation for Backplane Ethernet functions ............................................. 111

120. Physical Medium Attachment (PMA) sublayer, type 200GBASE-R and 400GBASE-R.................. 112

120.5 Functions within the PMA.......................................................................................................... 112

120.5.7 PAM4 Encoding Gray mapping for PAM4 encoded lanes................................................ 112

120.5.7.1 Gray mapping for PAM4 encoded lanes................................................................... 112

120.5.7.2 Precoding for PAM4 encoded lanes ......................................................................... 112

120.6 PMA MDIO function mapping................................................................................................... 112

120.7 Protocol implementation conformance statement (PICS) proforma for Clause 120, Physical

Medium Attachment (PMA) sublayer, type 200GBASE-R and 400GBASE-R ...................... 113

120.7.7 Encoding ............................................................................................................................ 113

131. Introduction to 50 Gb/s networks ....................................................................................................... 114

131.1 Overview..................................................................................................................................... 114

131.1.1 Scope.................................................................................................................................. 114

131.1.2 Relationship of 50 Gigabit Ethernet to the ISO OSI reference model............................... 114

131.1.3 Nomenclature..................................................................................................................... 114

131.1.4 Physical Layer signaling systems ...................................................................................... 116

131.2 Summary of 50 Gigabit Ethernet sublayers................................................................................ 117

131.2.1 Reconciliation Sublayer (RS) and Media Independent Interface (50GMII)...................... 117

131.2.2 Physical Coding Sublayer (PCS) ....................................................................................... 117

131.2.3 Forward Error Correction (FEC) sublayer......................................................................... 117

131.2.4 Physical Medium Attachment (PMA) sublayer................................................................. 117

131.2.5 Physical Medium Dependent (PMD) sublayer .................................................................. 117

131.2.6 Management interface (MDIO/MDC) ............................................................................... 117

131.2.7 Management....................................................................................................................... 118

131.3 Service interface specification method and notation .................................................................. 118

131.3.1 Inter-sublayer service interface.......................................................................................... 118

131.3.2 Instances of the Inter-sublayer service interface................................................................ 118

131.3.3 Semantics of inter-sublayer service interface primitives................................................... 118

131.4 Delay constraints......................................................................................................................... 120

131.5 Skew constraints ......................................................................................................................... 120

131.6 State diagrams............................................................................................................................. 123

131.7 Protocol implementation conformance statement (PICS) proforma........................................... 123

132. Reconciliation Sublayer (RS) and Media Independent Interface (50GMII) for 50 Gb/s operation ... 124

132.1 Overview..................................................................................................................................... 124

132.1.1 Summary of major concepts .............................................................................................. 124

132.1.2 Application......................................................................................................................... 124

132.1.3 Rate of operation................................................................................................................ 124

132.1.4 Delay constraints................................................................................................................ 125

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132.1.5 Allocation of functions ...................................................................................................... 126

132.1.6 50GMII structure ............................................................................................................... 126

132.1.7 Mapping of 50GMII signals to PLS service primitives..................................................... 126

132.2 50GMII data stream .................................................................................................................... 126

132.3 50GMII functional specifications ............................................................................................... 126

132.4 LPI assertion and detection......................................................................................................... 126

132.5 Protocol implementation conformance statement (PICS) proforma for Clause 132,

Reconciliation Sublayer (RS) and Media Independent Interface (50GMII) for 50 Gb/s

operation ................................................................................................................................... 127

132.5.1 Introduction........................................................................................................................ 127

132.5.2 Identification...................................................................................................................... 127

132.5.2.1 Implementation identification................................................................................... 127

132.5.2.2 Protocol summary..................................................................................................... 127

132.5.2.3 Major capabilities/options ........................................................................................ 128

132.5.3 PICS proforma tables for Reconciliation Sublayer (RS) and Media Independent

Interface (50GMII) for 50 Gb/s operation ........................................................................ 128

132.5.3.1 General ..................................................................................................................... 128

132.5.3.2 Mapping of PLS service primitives .......................................................................... 128

133. Physical Coding Sublayer (PCS) for 64B/66B, type 50GBASE-R .................................................... 129

133.1 Overview..................................................................................................................................... 129

133.1.1 Scope.................................................................................................................................. 129

133.1.2 Relationship of 50GBASE-R to other standards ............................................................... 129

133.1.3 Summary of 50GBASE-R sublayers ................................................................................. 129

133.1.3.1 Physical Coding Sublayer (PCS) .............................................................................. 129

133.1.4 Inter-sublayer interfaces .................................................................................................... 129

133.1.4.1 PCS service interface (50GMII) ............................................................................... 129

133.1.4.2 Forward Error Correction (FEC) or Physical Medium Attachment (PMA)

service interface ...................................................................................................... 130

133.1.5 Functional block diagram .................................................................................................. 131

133.2 Physical Coding Sublayer (PCS) ................................................................................................ 132

133.2.1 Functions within the PCS .................................................................................................. 132

133.2.2 Alignment marker insertion............................................................................................... 132

133.2.3 PCS lane deskew................................................................................................................ 133

133.2.4 Detailed functions and state diagrams ............................................................................... 133

133.3 Delay constraints......................................................................................................................... 133

133.4 Auto-Negotiation ........................................................................................................................ 133

133.5 Protocol implementation conformance statement (PICS) proforma for Clause 133, Physical

Coding Sublayer (PCS) for 64B/66B, type 50GBASE-R......................................................... 134

133.5.1 Introduction........................................................................................................................ 134

133.5.2 Identification...................................................................................................................... 134

133.5.2.1 Implementation identification................................................................................... 134

133.5.2.2 Protocol summary..................................................................................................... 134

133.5.3 Major capabilities/options.................................................................................................. 135

133.5.4 PICS proforma tables for Physical Coding Sublayer (PCS) for 64B/66B, type

50GBASE-R ..................................................................................................................... 135

133.5.4.1 Coding rules.............................................................................................................. 135

133.5.4.2 Scrambler and Descrambler...................................................................................... 136

133.5.4.3 Deskew and Reordering............................................................................................ 136

133.5.4.4 Alignment Markers ................................................................................................... 136

133.5.4.5 Test-pattern modes.................................................................................................... 136

133.5.4.6 Bit order .................................................................................................................... 137

133.5.4.7 Management.............................................................................................................. 137

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133.5.4.8 State diagrams........................................................................................................... 137

133.5.4.9 Loopback ................................................................................................................. 138

133.5.4.10 Delay constraints..................................................................................................... 138

133.5.4.11 Auto-Negotiation for Backplane Ethernet functions ............................................. 138

134. Reed-Solomon Forward Error Correction (RS-FEC) sublayer for 50GBASE-R PHYs .................... 139

134.1 Overview..................................................................................................................................... 139

134.1.1 Scope.................................................................................................................................. 139

134.1.2 Position of RS-FEC in the 50GBASE-R sublayers ........................................................... 139

134.2 FEC service interface.................................................................................................................. 139

134.3 PMA compatibility ..................................................................................................................... 140

134.4 Delay constraints......................................................................................................................... 141

134.5 Functions within the RS-FEC sublayer ...................................................................................... 141

134.5.1 Functional block diagram .................................................................................................. 141

134.5.2 Transmit function............................................................................................................... 141

134.5.2.1 PCS Lane block synchronization.............................................................................. 141

134.5.2.2 PCS Alignment lock and deskew.............................................................................. 141

134.5.2.3 PCS Lane reorder...................................................................................................... 141

134.5.2.4 Alignment marker removal....................................................................................... 141

134.5.2.5 64B/66B to 256B/257B transcoder........................................................................... 142

134.5.2.6 Alignment marker mapping and insertion ................................................................ 143

134.5.2.7 Reed-Solomon encoder............................................................................................. 144

134.5.2.8 Symbol distribution................................................................................................... 144

134.5.2.9 Transmit bit ordering ................................................................................................ 144

134.5.3 Receive function ................................................................................................................ 144

134.5.3.1 Alignment lock and deskew...................................................................................... 144

134.5.3.2 FEC Lane reorder...................................................................................................... 146

134.5.3.3 Reed-Solomon decoder............................................................................................. 146

134.5.3.3.1 FEC Error indication bypass (optional) ........................................................... 146

134.5.3.3.2 FEC Degraded SER (optional) ........................................................................ 147

134.5.3.4 Alignment marker removal....................................................................................... 147

134.5.3.5 256B/257B to 64B/66B transcoder........................................................................... 147

134.5.3.6 Block distribution ..................................................................................................... 147

134.5.3.7 Alignment marker mapping and insertion ................................................................ 147

134.5.3.8 Receive bit ordering.................................................................................................. 148

134.5.4 Detailed functions and state diagrams ............................................................................... 148

134.5.4.1 State diagram conventions ........................................................................................ 148

134.5.4.2 State variables ........................................................................................................... 150

134.5.4.2.1 Variables .......................................................................................................... 150

134.5.4.2.2 Functions.......................................................................................................... 150

134.5.4.2.3 Counters........................................................................................................... 150

134.5.4.3 State diagrams........................................................................................................... 150

134.6 RS-FEC MDIO function mapping.............................................................................................. 151

134.6.1 FEC_bypass_indication_enable......................................................................................... 152

134.6.2 FEC_degraded_SER_enable.............................................................................................. 152

134.6.3 FEC_degraded_SER_activate_threshold........................................................................... 152

134.6.4 FEC_degraded_SER_deactivate_threshold ....................................................................... 152

134.6.5 FEC_degraded_SER_interval ............................................................................................ 152

134.6.6 FEC_bypass_indication_ability ......................................................................................... 152

134.6.7 hi_ser.................................................................................................................................. 153

134.6.8 FEC_degraded_SER_ability.............................................................................................. 153

134.6.9 FEC_degraded_SER .......................................................................................................... 153

134.6.10 fec_optional_states........................................................................................................... 153

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