2922 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 23, NO. 12, DECEMBER 2015
Noise Modeling and Analysis of SAR ADCs
Wenpian Paul Zhang and Xingyuan Tong, Member, IEEE
Abstract—A generic statistical model for calculating
input-referred noise of an analog-to-digital converter (ADC)
impaired by thermal noise is proposed. Based on this model,
detailed statistical analyses are performed on three successive
approximation register (SAR) ADCs and the analytical results
obtained are verified with Monte Carlo simulations. To compare
the input-referred noise of different SAR ADC architectures,
a noise gain factor is proposed, which relates the noise at
the comparator input (top plate of capacitor array) to that
at the ADC input. The noise gain factors are computed
and compared for all three ADCs analyzed. The model and
methodology presented in this paper can be applied to various
ADC architectures for circuit design and optimization.
Index Terms—Analog-to-digital converter (ADC), noise,
successive approximation register (SAR), switched capacitor.
I. INTRODUCTION
S
UCCESSIVE approximation register (SAR) analog-to-
digital converters (ADCs) are employed in a wide range
of signal acquisition applications due to their high power
efficiency [1]–[6]. A survey of the references in [1] reveals
a puzzling, if not disconcerting fact that a detailed theoretical
treatment of noise does not exist in the literature.
A typical SAR ADC [7] operates in two phases, the
sampling phase and the bit-cycling (BC) phase. The noise
acquired during the sampling phase is trivially kT/C
tot
,where
C
tot
is the total capacitance of the capacitor array. For a
C
tot
= 1 pF, this noise voltage is 64 μV. In the BC phase,
successive bits are resolved one-by-one by the comparator.
The noise affecting the comparator outputs consists of two
components. The first component is the capacitor array’s
thermal noise, which is similar to that in the sampling phase
(64 μVforaC
tot
= 1 pF). The second component is the com-
parator’s intrinsic noise, which is 10 times higher (0.5–2 mV)
as seen in many comparator noise measurements [8]–[12].
Considering all these noise contributions in the ADC, the
noise power from the comparator in the BC phase is the most
dominant by a factor of 100 or so over the others. Therefore, it
Manuscript received July 31, 2014; revised October 21, 2014; accepted
December 4, 2014. Date of publication December 30, 2014; date of current
version November 20, 2015. This work was supported in part by the Natural
Science Foundation of Shanxi Province under Grant 2014JQ8332, in part by
the National Natural Science Foundation of China under Grant 61204029,
and in part by the National High-Tech Research and Development Program
of China under Grant 2013AA014504.
W. P. Zhang is with the Design Group, Synopsys, Inc., Shanghai 200050,
China (e-mail: zhangwe@yahoo.com).
X. Tong is with the Communication ASIC Design Engineering Center, Xi’an
University of Posts and Telecommunications, Xi’an 710121, China (e-mail:
mayxt@126.com).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TVLSI.2014.2379613
is of paramount theoretical and practical importance to study
the noise contribution of the comparator in the BC phase
to the total noise of the ADC. One may naively assume
this comparator noise refers to the input of the ADC with
a gain of unity (i.e., a 1-mV comparator noise refers to the
ADC input as 1 mV) and conclude that the noise analysis of
the simple SAR ADC in [7] is complete. However, this unity
gain assumption has absolutely no theoretical basis other than
it is a convenient one to be used for calculation.
Despite the lack of rigorous noise analysis and more
importantly, the lack of quantitative understanding of the noise
mechanism in the BC phase, numerous ingenious schemes
have nevertheless been invented that provide improved
comparator offset and noise tolerance. In [13], an extra cycle
is added to the analog-to-digital (A/D) conversion with the
last 2 bit cycles performed with a lower noise comparator.
Digital correction is then employed to obtain the final code.
This scheme is further discussed and generalized in [14]–[16].
In [17], the ADC operates similarly to the 1.5-bit pipeline
ADC [18]. Though the primary design objective was to
reduce the switching energy of the capacitive digital-to-analog
converter (DAC), this 1.5-bit SAR ADC nevertheless exhibits
a reduced input-referred noise compared with the conventional
one in [7]. In [19], the capacitive DAC array is designed with
a scaling factor less than 2. This subradix-2 scaling allows
some small amount of errors made in the conversion process
to be digitally corrected, hence reducing noise in the ADC.
An addition-only digital error correction scheme is proposed
in [20], which can tolerate some amount of settling errors
of the capacitive DAC. All of the above schemes exploit
redundancy to lower the impact of comparator noise on the
performance of the ADCs. However, no quantitative studies
of the noise impacts were provided in [13]–[20].
This paper attempts to provide an in-depth study of the
noise existing in SAR ADCs. This paper is organized as
follows. Section II presents a generic mathematical model for
calculating the input-referred noise of an ADC. In Section III,
detailed analyses of three representative SAR ADCs are pro-
vided and corroborated with Monte Carlo simulations. A gain
factor for noise is proposed for comparison of input-referred
noise in different SAR ADC architectures in Section IV. The
gain factors for all three ADCs considered are computed and
compared, followed by a discussion of how this factor is used
in SAR ADC designs. Section V concludes this paper.
II. N
OISE MODEL
An ADC is a nonlinear and probabilistic system, due
to the quantizer and physical noise present during the
A/D conversion process. Referring the noise within the
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