ModelSim命令参考手册10.5c：TCL命令解析与新手指南

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"ModelSim_command reference manual 10.5c.pdf" 《ModelSim 命令参考手册 10.5c》是Mentor Graphics公司官方发布的一份技术文档，旨在详细介绍ModelSim仿真软件中的TCL命令及其用法。这份手册对于使用者，尤其是新手来说，具有很高的学习价值和实用性。 ModelSim是一款广泛应用于数字电路系统级验证的仿真器，支持VHDL、Verilog等多种硬件描述语言。手册中包含的内容主要分为以下几个部分： 1. **TCL命令详解**：TCL（Tool Command Language）是一种脚本语言，ModelSim通过TCL提供了一套丰富的命令集，用于控制仿真流程、设置参数、调试设计等。手册中会详细解释每个TCL命令的语法、参数及用途，例如`vsim`用于启动仿真，`run`用于执行仿真，`add_source`用于添加设计文件等。 2. **工作环境管理**：包括如何创建和管理工程，设置仿真工作空间，导入和组织设计文件，以及配置编译和仿真选项。 3. **仿真控制**：涵盖如何启动和停止仿真，设置仿真时间，控制仿真步进，以及使用波形查看器观察信号状态。 4. **错误和警告处理**：介绍如何理解和解决在编译和仿真过程中遇到的问题，以及如何调试设计。 5. **高级特性**：如批处理模式操作、自定义脚本编写、性能优化策略等，这些内容能够帮助用户提高工作效率，实现更复杂的自动化任务。 6. **版权和法律信息**：文档中提及的版权和法律条款，规定了文档的使用限制，指出只有原始接收者才能复制此文档，并且必须防止未经授权的使用和分发。重要的是，由于Mentor Graphics有权随时更改产品规格和信息，因此手册的内容仅作为当前版本的参考，读者在使用时应与Mentor Graphics确认最新的信息和变更。此外，产品的销售和许可条件是通过书面协议在Mentor Graphics与其客户之间确定的，手册中的任何声明都不构成保修或承诺。《ModelSim 命令参考手册 10.5c》是深入理解和熟练使用ModelSim进行数字系统验证的必备参考资料，无论是初学者还是经验丰富的工程师，都能从中受益匪浅。通过阅读和实践手册中的内容，用户可以提升其在ModelSim环境下的操作技能，更高效地完成设计验证工作。

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ModelSim® Command Reference Manual, v10.5c

Syntax and Conventions

Tcl Syntax and Specification of Array Bits and Slices

and specified array element with curly braces ( {} ). Refer to Tcl Syntax and

Specification of Array Bits and Slices for important information about using square

brackets and parentheses in ModelSim commands.

o Array slicing — Slices (or part-selects) of arrays are specified using either

parentheses ( () ) or square brackets ( [] ) around a range specification. A range is

two numbers separated by one of the following: " to ", " downto ", or a colon ( : ).

You must also surround the object and specified array slice with curly braces ( {} ).

Refer to Tcl Syntax and Specification of Array Bits and Slices for important

information about using square brackets and parentheses in ModelSim commands.

o Record field selection — A record field is specified using a period ( . ) followed by

the name of the field.

Tcl Syntax and Specification of Array Bits and

Slices

Because ModelSim is based on the Tcl scripting language, you must surround objects and

signals with braces ( {} ) when specifying array bits or slices with parentheses ( () ), spaces, or

square brackets ( [] ).

For example:

toggle add {data[3:0]}

toggle add {data(3 to 0)}

force {bus1[1]} 1

Further Details

Because ModelSim is based on Tcl, its commands follow Tcl syntax. One problem you may

encounter with ModelSim commands is the use of square brackets ( [] ), parentheses ( () ), or

spaces when specifying array bits and slices. As noted, square brackets specify slices of arrays

(for example, data[3:0]). However, in Tcl, square brackets signify command substitution.

Consider the following example:

set aluinputs [find -in alu/*]

ModelSim evaluates the find command first and then sets variable aluinputs to the result of the

find command. Obviously, you do not want this type of behavior when specifying an array slice,

so you would use brace escape characters, as follows:

add wave {/s/abc/data_in[10:1]}

You must also use the escape characters if using VHDL syntax with spaces:

add wave {/s/abc/data_in(10 downto 1)}

ModelSim® Command Reference Manual, v10.5c

Syntax and Conventions

Specifying Names

Return the contents of the first element of the instance-specific array b.

When referring to the contents of a package or class, you cannot use the standard path

separators, a period ( . ) or a forward slash ( / ).

Specifying Names

ModelSim distinguishes between four "types" of object names: simple, relative, fully-rooted,

and absolute.

• Simple name — does not contain any hierarchy. It is simply the name of an object

(suchas clk or data[3:0]) in the current context.

• Relative name — does not start with a path separator and may or may not include a

dataset name or a hierarchical path (such as u1/data or view:clk). A relative name is

relative to the current context in the current or specified dataset.

• Fully-rooted name — starts with a path separator and includes a hierarchical path to an

object (e.g., /top/u1/clk).There is a special case of a fully-rooted name where the top-

level design unit name can be unspecified (such as /u1/clk). In this case, the first top-

level instance in the design is assumed.

• Absolute name — is an exactly specified hierarchical name containing a dataset name

and a fully rooted name (such as sim:/top/u1/clk).

The current dataset is used when accessing objects where a dataset name is not specified as part

of the name. The current dataset is determined by the dataset currently selected in the Structure

window or by the last dataset specified in an environment.

The current context in the current or specified dataset is used when accessing objects with

relative or simple names. The current context is either the current process, if any, or the current

instance if there is no current process, or the current process is not in the current instance. The

situation of the current process not being in the current instance can occur, for example, by

selecting a different instance in the Structure tab or by using the environment to set the current

context to a different instance.

The current context is also the activation level of an automatic task, function, or block. Different

levels of activation may be selected by using the Call Stack window, or by using the 'stack up' or

'stack down' commands.

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