多级非易失存储器：数字化应用的新突破

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本文是一篇关于非易失性多级存储器在数字应用中的早期研究论文，由Bruno Ricco、Guido Torelli、Massimo Lanzoni、Alessandro Romatti、Herman Maes、Donato Montanari和Alberto Modelli等专家撰写。标题"Nonvolatile Multilevel Memories for Digital Applications"表明了该研究的核心关注点在于探索多级闪存（MLC）技术，这是一种非易失性的存储技术，旨在提高存储密度和信息存储能力，以满足日益增长的数字化需求。传统的半导体存储器通常将每个存储单元与一个二进制位关联，这种一对一的关系虽然直观，但在实际数据存储中并不总是最优方案。作者指出，通过利用模拟信号以及数字到模拟（D/A）和模拟到数字（A/D）转换，可以在一个存储单元中存储多个比特。这不仅可以显著增加存储密度，但同时也带来了信号噪声比（SNR）的问题，这是电子学中常见的挑战。文章探讨的核心议题是，在存储过程中如何权衡精度和实际应用中的限制。在理想情况下，完全数字化的方法追求无限精确的模拟存储，即每个细胞可存储无限数量的比特，但这在现实中难以实现。因此，多级存储（如MLC）作为一种折衷方案被提出，它通过使用多个电压或电荷水平来表示不同的数据状态，允许在有限的空间内存储更多信息，同时处理好信号质量与密度之间的平衡。 MLC技术通过多层次的编码，比如4层（QLC）、3层（QLP）甚至更高，提高了存储密度，使得单个闪存芯片可以存储更多的数据，这对于移动设备、固态硬盘等存储设备的容量扩展至关重要。然而，这也带来了复杂性，包括更复杂的电路设计、更高的错误率管理和更精细的读写操作控制。这篇文章深入剖析了非易失性多级存储器在数字化应用中的潜在优势和挑战，对于理解现代存储技术的发展趋势和优化存储器设计具有重要意义。同时，它也为工程师们提供了关于如何在性能和成本之间进行权衡的思考空间，以适应不断变化的市场需求。

The worst case occurs for the bit-line disturb on a cell

programmed to the highest

level because of the large

shift with respect to the neutral state. Moreover, pro-

gramming the drain voltage is the same as in conventional

Flash memories but the time is longer. On the contrary,

word-line disturb should not be affected substantially by

the increase in program time, at least for a staircase gate-

voltage programming algorithm, since during most of the

time the word-line voltage is rather low and only the

last few pulses will effectively contribute to the disturb.

Optimized cell design for low drain voltage programming

and divided bit-line organization are probably required to

guarantee sufﬁcient program disturb immunity.

As for reading, the operation essentially can be consid-

ered as an analog-to-digital (A/D) conversion of the signal

produced by the addressed cell, and the key issue concerns

the tradeoff between speed and accuracy, in that as the

latter is increased (i.e., as smaller values of

can

be safely recognized) a larger number of bits can be stored

on a single cell, but the sensing circuitry becomes more

expensive and globally slower. In general, the required A/D

conversion can be done in parallel or sequentially for higher

speed and smaller area occupation, respectively, while

intermediate solutions offer interesting tradeoffs between

these conﬂicting aspects.

With regard to reliability, instead, the crucial problem of

data retention is better expressed in terms of the number

of stored electrons. With FG capacitances in the 10

F range, threshold voltage windows of a few require

variations of about 30 000 electrons in the FG. If this

variation is split, for instance, in four levels, the states of the

sense transistors differ from one another by about 10000

electrons, and this difference should be maintained for more

than ten years. This implies that less than about 1 000

electrons should leak out from (or into) the FG in one year,

i.e., that the (average) leakage currents through the oxide

insulating the FG should be smaller than 10

A (or, about

A/cm ). Of course, this problem is signiﬁcantly

aggravated if the number of levels programmed in a cell

is increased and/or the total

window is narrowed.

The problem can (and must) be alleviated in part with

the use of redundancy- and error-detecting codes, but the

very small numbers given above clearly indicate the need of

outstanding insulating properties. From this point of view,

stress-induced leakage current (SILC), i.e., the excess low-

ﬁeld conductivity of the oxide induced by the high ﬁeld

stress used during tunnel programming [22], [23] and/or

oxide time-dependent breakdown poses serious problems.

In any case, MLM’s must meet much more stringent

requirements than conventional bilevel memories in terms

of threshold voltage distribution for each stored level, data

retention, program/read disturb immunity, and design issues

(namely, sense and program accuracies) [21], [24], [25].

D. Problem Interaction

The successful realization of MLM’s and the number

of bits that can be stored in a single cell depend on the

solutions given to the main problems mentioned above

(accurate charge placement, cell sensing, and reliability).

Such solutions, however, are strongly dependent on the

physical mechanism used for cell writing as well as on

the memory architectures, which are fundamental ingre-

dients determining the complexity, performance, and cost

effectiveness of memory chips.

Thus, the realization of MLM’s represents a unique

global problem composed of many interacting aspects that

must be considered concurrently in the conception and

development of real products, as well as in the analysis

of the subject, as is done in the rest of this paper.

II. B

ASICS IN NV MEMORIES

A. Writing Mechanisms

MLM’s make use of the same physical mechanisms

for injecting and/or extracting electrons from the FG as

their conventional (i.e., bilevel) counterparts, namely CHE

injection and FN tunneling, while UV exposure can also

be used for erasing. ML operation, however, has more

stringent requirements since it needs accurate control of

the

distributions of the different levels, which must not

only be narrow but also well separated.

CHE injection and FN tunneling present speciﬁc features

that interact strongly with circuit and architectural aspects;

these are brieﬂy reviewed below.

The CHE mechanism enables electrons to be injected

into the cell FG by applying a suitable medium–high drain

voltage (to heat the electrons within the transistor channel)

and a high gate voltage, providing both adequate electron

density in the channel and sufﬁcient electric ﬁeld in the

gate oxide (

, in any case signiﬁcantly lower than that

required for FN tunneling).

The injection efﬁciency of CHE injection is very small,

as the current ﬂowing through the gate oxide is only a very

small fraction of the cell-drain current. Typical values of

drain currents during programming are in the range of a few

hundred

A per cell, although an optimized cell structure

can operate with currents around 100

A or less [26], while

the average current injected into the gate oxide

is in

the range of 0.1 to 1 nA.

Naturally, it is not possible to heat electrons within the

FG by means of an electric ﬁeld; thus the hot electron

mechanism cannot be used to extract electrons from it.

FN tunneling, instead, allows injection of cold carriers

and gives rise to a current ﬂowing into (or from) the FG,

that exhibits a (quasi) exponential dependence on

and

can be reversed by simply changing the sign of such a

ﬁeld; thus it can be used for both injection and extraction

of electrons into/from the FG. For these operations to be

completed in practical times, a very high ﬁeld is needed (in

the range of 8–10 MV/cm), which gives rise to reliability

problems ultimately limiting the writing speed, while the

high voltages required to generate adequate ﬁelds are not

easy to handle at the circuit level.

Two different FN tunneling schemes are of interest for

NV memories. In the ﬁrst one (channel FN tunneling),

RICC

O et al.: NONVOLATILE MULTILEVEL MEMORIES 2403

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