TI MSP430F54xx 系列微控制器数据手册与资源

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"MSP430系列微控制器的相关资料，特别是MSP430F5418a的数据手册，涵盖了多个型号如MSP430F5438A, MSP430F5437A等。这份资料来源于www.ti.com，更新于2013年，提供了该系列芯片的主要特性和功能，包括低功耗、多种定时器和串行通信接口等。" MSP430系列是由德州仪器（TI）开发的一系列超低功耗的16位微控制器，广泛应用于各种嵌入式系统中，如传感器节点、便携式设备和物联网应用。MSP430F5418a是其中的一个型号，它具有以下关键特性： 1. **低供电电压范围**：MSP430F5418a可以在1.8V至3.6V的宽电压范围内工作，这使得它适合在电池供电或电源受限的环境中使用。它还配备了一个低频校准的内部参考源（REFO），可以在低电压下保持精度。 2. **超低功耗**：在主动模式（AM）下，即使所有系统时钟都处于活动状态，MSP430F5418a也能实现低功耗运行。此外，还有待机模式（LPM3），在此模式下，如RTC、看门狗和电源监控器依然工作，但能显著降低功耗，快速唤醒功能确保了高效能与节能的平衡。 3. **定时器功能**：MSP430F5418a包含了多种定时器，如16位Timer_A（TA0、TA1）和Timer_B（TB0）。它们带有捕获/比较寄存器，可执行不同任务，如脉冲宽度调制（PWM）、计数和中断管理。例如，TA0和TA1在8MHz、3.0V时的功耗分别为230µA/MHz和110µA/MHz，提供高效率的定时操作。 4. **串行通信接口**：MSP430F5418a支持多达四个通用串行通信接口（USCI_A0, USCI_A1, USCI_A2, USCI_A3），能够兼容I2C、SPI和UART等多种通信协议，便于与其他设备进行数据交换。 5. **其他功能**：除了上述特点，MSP430F5418a还包括了丰富的外围设备，如实时时钟（RTC）、看门狗定时器以及电源监视器，确保系统的稳定性和可靠性。在设计嵌入式系统时，选择MSP430F5418a这类微控制器可以实现高性能、低功耗的目标。通过数据手册，开发者可以了解到每个引脚的功能、内存配置、中断系统、模拟和数字外设等详细信息，从而有效地进行硬件设计和软件编程。此外，TI官方网站提供的最新文档和样本服务，对于开发者来说是非常宝贵的资源，可以帮助他们获取最新的技术信息和支持。

MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A

MSP430F5419A, MSP430F5418A

SLAS655D –JANUARY 2010–REVISED AUGUST 2013

www.ti.com

Interrupt Vector Addresses

The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h. The

vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.

Table 3. Interrupt Sources, Flags, and Vectors

SYSTEM WORD

INTERRUPT SOURCE INTERRUPT FLAG PRIORITY

INTERRUPT ADDRESS

System Reset

Power-Up

External Reset

Watchdog Timeout, Password WDTIFG, KEYV (SYSRSTIV)

(1) (2)

Reset 0FFFEh 63, highest

Violation

Flash Memory Password Violation

PMM Password Violation

System NMI

SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG,

PMM

VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG, (Non)maskable 0FFFCh 62

Vacant Memory Access

JMBOUTIFG (SYSSNIV)

(1)

JTAG Mailbox

User NMI

NMI

NMIIFG, OFIFG, ACCVIFG (SYSUNIV)

(1) (2)

(Non)maskable 0FFFAh 61

Oscillator Fault

Flash Memory Access Violation

TB0 TBCCR0 CCIFG0

(3)

Maskable 0FFF8h 60

TBCCR1 CCIFG1 to TBCCR6 CCIFG6,

TB0 Maskable 0FFF6h 59

TBIFG (TBIV)

(1) (3)

Watchdog Timer_A Interval Timer

WDTIFG Maskable 0FFF4h 58

Mode

USCI_A0 Receive and Transmit UCA0RXIFG, UCA0TXIFG (UCA0IV)

(1) (3)

Maskable 0FFF2h 57

USCI_B0 Receive and Transmit UCB0RXIFG, UCB0TXIFG (UCB0IV)

(1) (3)

Maskable 0FFF0h 56

ADC12_A ADC12IFG0 to ADC12IFG15 (ADC12IV)

(1) (3)

Maskable 0FFEEh 55

TA0 TA0CCR0 CCIFG0

(3)

Maskable 0FFECh 54

TA0CCR1 CCIFG1 to TA0CCR4 CCIFG4,

TA0 Maskable 0FFEAh 53

TA0IFG (TA0IV)

(1) (3)

USCI_A2 Receive and Transmit UCA2RXIFG, UCA2TXIFG (UCA2IV)

(1) (3)

Maskable 0FFE8h 52

USCI_B2 Receive and Transmit UCB2RXIFG, UCB2TXIFG (UCB2IV)

(1) (3)

Maskable 0FFE6h 51

DMA DMA0IFG, DMA1IFG, DMA2IFG (DMAIV)

(1) (3)

Maskable 0FFE4h 50

TA1 TA1CCR0 CCIFG0

(3)

Maskable 0FFE2h 49

TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2,

TA1 Maskable 0FFE0h 48

TA1IFG (TA1IV)

(1) (3)

I/O Port P1 P1IFG.0 to P1IFG.7 (P1IV)

(1) (3)

Maskable 0FFDEh 47

USCI_A1 Receive and Transmit UCA1RXIFG, UCA1TXIFG (UCA1IV)

(1) (3)

Maskable 0FFDCh 46

USCI_B1 Receive and Transmit UCB1RXIFG, UCB1TXIFG (UCB1IV)

(1) (3)

Maskable 0FFDAh 45

USCI_A3 Receive and Transmit UCA3RXIFG, UCA3TXIFG (UCA3IV)

(1) (3)

Maskable 0FFD8h 44

USCI_B3 Receive and Transmit UCB3RXIFG, UCB3TXIFG (UCB3IV)

(1) (3)

Maskable 0FFD6h 43

I/O Port P2 P2IFG.0 to P2IFG.7 (P2IV)

(1) (3)

Maskable 0FFD4h 42

RTCRDYIFG, RTCTEVIFG, RTCAIFG,

RTC_A Maskable 0FFD2h 41

RT0PSIFG, RT1PSIFG (RTCIV)

(1) (3)

0FFD0h 40

Reserved Reserved

(4)

⋮ ⋮

0FF80h 0, lowest

(1) Multiple source flags

(2) A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.

(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.

(3) Interrupt flags are located in the module.

(4) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain

compatibility with other devices, it is recommended to reserve these locations.

Product Folder Links: MSP430F5438A MSP430F5437A MSP430F5436A MSP430F5435A MSP430F5419A

MSP430F5418A

MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A

MSP430F5419A, MSP430F5418A

www.ti.com

SLAS655D –JANUARY 2010–REVISED AUGUST 2013

Memory Organization

MSP430F5419A MSP430F5436A MSP430F5438A

MSP430F5418A MSP430F5435A MSP430F5437A

Memory (flash) Total Size 128 KB 192 KB 256 KB

Main: interrupt vector Flash 00FFFFh–00FF80h 00FFFFh–00FF80h 00FFFFh–00FF80h

Main: code memory Flash 025BFFh–005C00h 035BFFh–005C00h 045BFFh–005C00h

Bank D N/A 23 KB 64 KB

035BFFh–030000h 03FFFFh–030000h

Bank C 23 KB 64 KB 64 KB

025BFFh–020000h 02FFFFh–020000h 02FFFFh–020000h

Main: code memory

Bank B 64 KB 64 KB 64 KB

01FFFFh–010000h 01FFFFh–010000h 01FFFFh–010000h

Bank A 41 KB 41 KB 64 KB

00FFFFh–005C00h 00FFFFh–005C00h 045BFFh–040000h

00FFFFh–005C00h

Size 16 KB 16 KB 16 KB

Sector 3 4 KB 4 KB 4 KB

005BFFh–004C00h 005BFFh–004C00h 005BFFh–004C00h

Sector 2 4 KB 4 KB 4 KB

RAM 004BFFh–003C00h 004BFFh–003C00h 004BFFh–003C00h

Sector 1 4 KB 4 KB 4 KB

003BFFh–002C00h 003BFFh–002C00h 003BFFh–002C00h

Sector 0 4 KB 4 KB 4 KB

002BFFh–001C00h 002BFFh–001C00h 002BFFh–001C00h

Info A 128 B 128 B 128 B

0019FFh–001980h 0019FFh–001980h 0019FFh–001980h

Info B 128 B 128 B 128 B

00197Fh–001900h 00197Fh–001900h 00197Fh–001900h

Information memory

(flash)

Info C 128 B 128 B 128 B

0018FFh–001880h 0018FFh–001880h 0018FFh–001880h

Info D 128 B 128 B 128 B

00187Fh–001800h 00187Fh–001800h 00187Fh–001800h

BSL 3 512 B 512 B 512 B

0017FFh–001600h 0017FFh–001600h 0017FFh–001600h

BSL 2 512 B 512 B 512 B

0015FFh–001400h 0015FFh–001400h 0015FFh–001400h

Bootstrap loader (BSL)

memory (Flash)

BSL 1 512 B 512 B 512 B

0013FFh–001200h 0013FFh–001200h 0013FFh–001200h

BSL 0 512 B 512 B 512 B

0011FFh–001000h 0011FFh–001000h 0011FFh–001000h

Size 4KB 4KB 4KB

Peripherals

000FFFh–000000h 000FFFh–000000h 000FFFh–000000h

Product Folder Links: MSP430F5438A MSP430F5437A MSP430F5436A MSP430F5435A MSP430F5419A

MSP430F5418A

MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A

MSP430F5419A, MSP430F5418A

SLAS655D –JANUARY 2010–REVISED AUGUST 2013

www.ti.com

Bootstrap Loader (BSL)

The BSL enables users to program the flash memory or RAM using a UART serial interface. Access to the

device memory via the BSL is protected by an user-defined password. Usage of the BSL requires four pins as

shown in Table 4. BSL entry requires a specific entry sequence on the RST/NMI/SBWTDIO and TEST/SBWTCK

pins. For complete description of the features of the BSL and its implementation, see the MSP430 Memory

Programming via the Bootstrap Loader User's Guide (SLAU319).

Table 4. BSL Pin Requirements and Functions

DEVICE SIGNAL BSL FUNCTION

RST/NMI/SBWTDIO Entry sequence signal

TEST/SBWTCK Entry sequence signal

P1.1 Data transmit

P1.2 Data receive

VCC Power supply

VSS Ground supply

JTAG Operation

JTAG Standard Interface

The MSP430 family supports the standard JTAG interface which requires four signals for sending and receiving

data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to enable the

JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with MSP430

development tools and device programmers. The JTAG pin requirements are shown in Table 5. For further

details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's

Guide (SLAU278). For complete description of the features of the JTAG interface and its implementation, see the

MSP430 Memory Programming via the JTAG Interface User's Guide (SLAU320).

Table 5. JTAG Pin Requirements and Functions

DEVICE SIGNAL DIRECTION FUNCTION

PJ.3/TCK IN JTAG clock input

PJ.2/TMS IN JTAG state control

PJ.1/TDI/TCLK IN JTAG data input/TCLK input

PJ.0/TDO OUT JTAG data output

TEST/SBWTCK IN Enable JTAG pins

RST/NMI/SBWTDIO IN External reset

VCC Power supply

VSS Ground supply

Spy-Bi-Wire Interface

In addition to the standard JTAG interface, the MSP430 family supports the two wire Spy-Bi-Wire interface. Spy-

Bi-Wire can be used to interface with MSP430 development tools and device programmers. The Spy-Bi-Wire

interface pin requirements are shown in Table 6. For further details on interfacing to development tools and

device programmers, see the MSP430 Hardware Tools User's Guide (SLAU278). For the description of the Spy-

Bi-Wire interface and its implementation, see the MSP430 Memory Programming via the JTAG Interface User's

Guide (SLAU320).

Table 6. Spy-Bi-Wire Pin Requirements and Functions

DEVICE SIGNAL DIRECTION FUNCTION

TEST/SBWTCK IN Spy-Bi-Wire clock input

RST/NMI/SBWTDIO IN, OUT Spy-Bi-Wire data input/output

VCC Power supply

VSS Ground supply

Product Folder Links: MSP430F5438A MSP430F5437A MSP430F5436A MSP430F5435A MSP430F5419A

MSP430F5418A

MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A

MSP430F5419A, MSP430F5418A

www.ti.com

SLAS655D –JANUARY 2010–REVISED AUGUST 2013

Flash Memory (Link to User's Guide)

The flash memory can be programmed via the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the

CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory. Features of the

flash memory include:

• Flash memory has n segments of main memory and four segments of information memory (A to D) of

128 bytes each. Each segment in main memory is 512 bytes in size.

• Segments 0 to n may be erased in one step, or each segment may be individually erased.

• Segments A to D can be erased individually. Segments A to D are also called information memory.

• Segment A can be locked separately.

RAM Memory (Link to User's Guide)

The RAM memory is made up of n sectors. Each sector can be completely powered down to save leakage,

however all data is lost. Features of the RAM memory include:

• RAM memory has n sectors. The size of a sector can be found in Memory Organization.

• Each sector 0 to n can be complete disabled; however, data retention is lost.

• Each sector 0 to n automatically enters low-power retention mode when possible.

• For devices that contain USB memory, the USB memory can be used as normal RAM if USB is not required.

Peripherals

Peripherals are connected to the CPU through data, address, and control buses and can be handled using all

instructions. For complete module descriptions, see the MSP430x5xx and MSP430x6xx Family User's Guide

(SLAU208).

Digital I/O (Link to User's Guide)

There are up to ten 8-bit I/O ports implemented: For 100-pin options, P1 through P10 are complete. P11 contains

three individual I/O ports. For 80-pin options, P1 through P7 are complete. P8 contains seven individual I/O ports.

P9 through P11 do not exist. Port PJ contains four individual I/O ports, common to all devices.

• All individual I/O bits are independently programmable.

• Any combination of input, output, and interrupt conditions is possible.

• Pullup or pulldown on all ports is programmable.

• Drive strength on all ports is programmable.

• Edge-selectable interrupt and LPM4.5 wakeup input capability is available for all bits of ports P1 and P2.

• Read and write access to port-control registers is supported by all instructions.

• Ports can be accessed byte-wise (P1 through P11) or word-wise in pairs (PA through PF).

Product Folder Links: MSP430F5438A MSP430F5437A MSP430F5436A MSP430F5435A MSP430F5419A

MSP430F5418A

MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A

MSP430F5419A, MSP430F5418A

SLAS655D –JANUARY 2010–REVISED AUGUST 2013

www.ti.com

Oscillator and System Clock (Link to User's Guide)

The clock system is supported by the Unified Clock System (UCS) module that includes support for a 32-kHz

watch crystal oscillator (XT1 LF mode), an internal very-low-power low-frequency oscillator (VLO), an internal

trimmed low-frequency oscillator (REFO), an integrated internal digitally controlled oscillator (DCO), and a high-

frequency crystal oscillator (XT1 HF mode or XT2). The UCS module is designed to meet the requirements of

both low system cost and low power consumption. The UCS module features digital frequency locked loop (FLL)

hardware that, in conjunction with a digital modulator, stabilizes the DCO frequency to a programmable multiple

of the selected FLL reference frequency. The internal DCO provides a fast turn-on clock source and stabilizes in

less than 5 µs. The UCS module provides the following clock signals:

• Auxiliary clock (ACLK), sourced from a 32-kHz watch crystal, a high-frequency crystal, the internal low-

frequency oscillator (VLO), the trimmed low-frequency oscillator (REFO), or the internal digitally controlled

oscillator DCO.

• Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources made

available to ACLK.

• Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be sourced by

same sources made available to ACLK.

• ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32.

Power Management Module (PMM) (Link to User's Guide)

The PMM includes an integrated voltage regulator that supplies the core voltage to the device and contains

programmable output levels to provide for power optimization. The PMM also includes supply voltage supervisor

(SVS) and supply voltage monitoring (SVM) circuitry, as well as brownout protection. The brownout circuit is

implemented to provide the proper internal reset signal to the device during power-on and power-off. The SVS

and SVM circuitry detects if the supply voltage drops below a user-selectable level and supports both supply

voltage supervision (the device is automatically reset) and supply voltage monitoring (the device is not

automatically reset). SVS and SVM circuitry is available on the primary supply and core supply.

Hardware Multiplier (MPY) (Link to User's Guide)

The multiplication operation is supported by a dedicated peripheral module. The module performs operations with

32-bit, 24-bit, 16-bit, and 8-bit operands. The module is capable of supporting signed and unsigned multiplication

as well as signed and unsigned multiply and accumulate operations.

Real-Time Clock (RTC_A) (Link to User's Guide)

The RTC_A module can be used as a general-purpose 32-bit counter (counter mode) or as an integrated real-

time clock (RTC) (calendar mode). In counter mode, the RTC_A also includes two independent 8-bit timers that

can be cascaded to form a 16-bit timer/counter. Both timers can be read and written by software. Calendar mode

integrates an internal calendar which compensates for months with less than 31 days and includes leap year

correction. The RTC_A also supports flexible alarm functions and offset-calibration hardware.

Watchdog Timer (WDT_A) (Link to User's Guide)

The primary function of the watchdog timer (WDT_A) module is to perform a controlled system restart after a

software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog

function is not needed in an application, the module can be configured as an interval timer and can generate

interrupts at selected time intervals.

Product Folder Links: MSP430F5438A MSP430F5437A MSP430F5436A MSP430F5435A MSP430F5419A

MSP430F5418A

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