"STM32MP153C数据手册：Arm®双核心处理器，高级功能模块详解"

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The STM32MP153C datasheet provides preliminary information on a new product currently in development or undergoing evaluation. This datasheet is from 3 August 2018 and is subject to change without notice. The STM32MP153Cxx is an Arm® dual Cortex®-A7 650 MHz Cortex®-M4 MPU with TFT, 37 communication interfaces, 29 timers, advanced analog features, and crypto capabilities. The core features of the STM32MP153Cxx include a 32-bit dual-core Arm® Cortex®-A7 processor with 32-Kbyte instruction and data caches for each core, as well as a 256-Kbyte unified level 2 cache. The MPU also includes: - Multiple communication interfaces for versatile connectivity options. - A large number of timers for precise timing control. - Advanced analog capabilities for signal processing. - Crypto functionality for secure data handling. Overall, the STM32MP153Cxx offers a powerful combination of processing power, communication options, timing control, analog features, and security capabilities. This product is still in the development phase, and details are subject to change as it undergoes evaluation.

Description STM32MP153Cxx

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Watchdog 3 (independent, independent secure, window) -

Communication peripherals

SPI 6 (1 securable)

Having I2S 3

I2C (with SMB/PMB support) 6 (2 securable) -

USART (smartcard, SPI, IrDA, LIN)

+ UART (IrDA, LIN)

4 + 4 (including 1 securable USART)

some can be a boot source

Boot

SAI

4 (up to 8 audio channels), with I2S master/slave, PCM input,

SPDIF-TX

Boot

USB

EHCI/OHCI Host

2 ports -

Embedded HS PHY with BCD -

OTG HS/FS

(dual role port)

Yes, embedded FS or HS PHY with BCD, can be a boot source Boot

Embedded PHYs 3 (2 × high-speed + 1 × full-speed) -

SPDIF-RX 4 inputs -

FDCAN 2 (1 × TTCAN), clock calibration, 10 Kbyte shared buffer -

HDMI-CEC 1 -

Including the following securable 1 × USART, 1 × SPI, 2 × I2C

1 × USART, 1 × SPI, 2 × I2C

on securable GPIOs

SDMMC (SD, SDIO, e•MMC) 3 (8 + 8 + 4 bits), e•MMC or SD can be a boot source Boot

QuadSPI Yes (dual-quad), can be a boot source Boot

FMC

Parallel address/data 8/16-bit - 4 × CS, up to 4 × 64 Mbyte

boot

Parallel AD-Mux 8/16-bit 4 × CS, up to 4 × 64 Mbytes

NAND 8/16-bit Yes, 1 × CS, SLC, BCH4/8, can be a boot source Boot

Gigabit Ethernet -

MII, RMII, GMII, RGMII with

PTP and EEE

10/100M Ethernet MII, RMII with PTP and EEE

LCD-TFT Parallel interface

up to 24-bit data

(up to 1366×768 60 fps)

DMA 3 instances (1 securable), 48 physical channels in total -

Cryptography

DES, TDES, AES-256

dual instances (secure and non-secure)

Hash

SHA-256, MD5, HMAC

dual instances (secure and non-secure)

True random number generator True-RNG, dual instances (secure and non-secure) -

Fuses (one-time programmable) 3072 effective bits (secure, >1500 bits available for user) -

Camera interface Bus width 14-bit -

Table 2. STM32MP153Cxx features and peripheral counts (continued)

Features

STM32MP153

CAD

TFBGA257

STM32MP153

CAB

LFBGA354

STM32MP153

CAC

TFBGA361

STM32MP153

CAA

LFBGA448

Miscella-

neous

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STM32MP153Cxx Functional overview

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3 Functional overview

3.1 Dual-core Arm

Cortex

-A7 subsystem

3.1.1 Features

• ARMv7-A architecture

• 32-Kbyte L1 instruction cache for each CPU

• 32-Kbyte L1 data cache for each CPU

• 256-Kbyte level2 cache

• Arm

+ Thumb

-2 instruction set

• Arm

TrustZone

security technology

• Arm

NEON™ Advanced SIMD

• DSP and SIMD extensions

• VFPv4 floating-point

• Hardware virtualization support

• Embedded trace module (ETM)

• Integrated generic interrupt controller (GIC) with 256 shared peripheral interrupts

• Integrated generic timer (CNT)

3.1.2 Overview

The Cortex-A7 processor is a very energy-efficient applications processor designed to

provide rich performance in high-end wearables, and other low-power embedded and

consumer applications. It provides up to 20 % more single thread performance than the

Cortex-A5 and provides similar performance than the Cortex-A9.

The Cortex-A7 incorporates all features of the high-performance Cortex-A15 and Cortex-

A17 processors, including virtualization support in hardware, NEON

™

, and 128-bit AMBA

AXI bus interface.

The Cortex-A7 processor builds on the energy-efficient 8-stage pipeline of the Cortex-A5

processor. It also benefits from an integrated L2 cache designed for low-power, with lower

transaction latencies and improved OS support for cache maintenance. On top of this, there

is improved branch prediction and improved memory system performance, with 64-bit load-

store path, 128-bit AMBA 4 AXI buses and increased TLB size (256 entry, up from 128 entry

for Cortex-A9 and Cortex-A5), increasing performance for large workloads such as web

browsing.

Thumb-2 technology

Delivers the peak performance of traditional Arm

code while also providing up to a 30 %

reduction in memory requirement for instructions storage.

TrustZone technology

Ensures reliable implementation of security applications ranging from digital rights

management to electronic payment. Broad support from technology and industry partners.

Functional overview STM32MP153Cxx

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NEON

NEON technology can accelerate multimedia and signal processing algorithms such as

video encode/decode, 2D/3D graphics, gaming, audio and speech processing, image

processing, telephony, and sound synthesis. The Cortex-A7 provides an engine that offers

both the performance and functionality of the Cortex-A7 floating-point unit (FPU) and an

implementation of the NEON advanced SIMD instruction set for further acceleration of

media and signal processing functions. The NEON extends the Cortex-A7 processor FPU to

provide a quad-MAC and additional 64-bit and 128-bit register set supporting a rich set of

SIMD operations over 8-, 16- and 32-bit integer and 32-bit floating-point data quantities.

Hardware virtualization

Highly efficient hardware support for data management and arbitration, whereby multiple

software environments and their applications are able to simultaneously access the system

capabilities. This enables the realization of devices that are robust, with virtual environments

that are well isolated from each other.

Optimized L1 caches

Performance and power optimized L1 caches combine minimal access latency techniques

to maximize performance and minimize power consumption. There is also the option of

cache coherence for enhanced inter-processor communication, or support of a rich SMP

capable OS for simplified multicore software development.

Integrated L2 cache controller

Provides low-latency and high-bandwidth access to cached memory in high-frequency, or to

reduce the power consumption associated with off-chip memory access.

Cortex-A7 floating-point unit (FPU)

The FPU provides high-performance single and double precision floating-point instructions

compatible with the Arm VFPv4 architecture that is software compatible with previous

generations of Arm floating-point coprocessor.

Snoop control unit (SCU)

The SCU is responsible for managing the interconnect, arbitration, communication, cache to

cache and system memory transfers, cache coherence and other capabilities for the

processor.

This system coherence also reduces software complexity involved in maintaining software

coherence within each OS driver.

Generic interrupt controller (GIC)

Implementing the standardized and architected interrupt controller, the GIC provides a rich

and flexible approach to inter-processor communication and the routing and prioritization of

system interrupts.

Supporting up to 288 independent interrupts, under software control, each interrupt can be

distributed across A7 cores, hardware prioritized, and routed between the operating system

and TrustZone software management layer.

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