ICN6201/02 Specification V1.0
1 Introduction
ICN6201/02 is a bridge chip which receives MIPI
®
DSI inputs and sends LVDS outputs.
MIPI
®
DSI supports up to 4 lanes and each lane operates at 1Gbps maximum; the totally maximum input
bandwidth is 4Gbps; and the MIPI defined ULPS(ultra-low-power state) is also supported. ICN6201 decodes
MIPI
®
DSI 18bepp RGB666 and 24bpp RGB888 packets.
The LVDS output 18 or 24 bits pixel with 25MHz to 154MHz, by VESA or JEIDA format.
ICN6201/02 support video resolution up to FHD (1920x1080) and WUXGA (1920x1200).
ICN6201 adopts QFN48 package and ICN6202 adopts QFN40 package.
1.1 Feature List
• Supports MIPI
®
D-PHY Version 1.00.00 and MIPI
®
DSI Version 1.02.00.
• Single Channel DSI Receiver with One, Two, Three and Four lanes configurable, each lanes operates up to
1Gbps.
• Receives 18bpp RGB666 and 24bpp RGB888 packets defined by DSI.
• Supports MIPI Low State, Ultra-Low Power State, Shut Down mode.
• Single Channel LVDS with output clock range of 25MHz to 154MHz.
• LVDS can be generated from MIPI HS clock or external reference clock.
• Support LVDS clock with center spreading up to 2%, modulation 30KHz ~ 60KHz.
• LVDS output with VESA or JEIDA format.
• LVDS output pin order can be swapped flexible.
• Supply voltage: 1.8V.
• Provide I2C slave interface.
• Package: ICN6201 QFN48-pins with e-pad.
• Package: ICN6202 QFN40-pins with e-pad.
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