SKHynix DDR3 SDRAM 规格书 Rev.1.2

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"DDR3_H5TQG83GFR是SK海力士(Hynix)生产的一款2Gb DDR3 SDRAM内存芯片，适用于需要大容量存储和高带宽的主内存应用。该芯片遵循DDR3规范，具有双倍数据速率同步动态随机存取存储器的特点，支持在时钟的上升沿和下降沿进行同步操作。产品系列包括H5TQ2G83GFR-xxC、H5TQ2G63GFR-xxC、H5TQ2G83GFR-xxI、H5TQ2G63GFR-xxI、H5TQ2G83GFR-xxJ、H5TQ2G63GFR-xxJ、H5TQ2G83GFR-xxL和H5TQ2G63GFR-xxL，且符合无铅和无卤素的RoHS标准。" DDR3内存技术详解： DDR3，全称为Double Data Rate Third Generation Synchronous Dynamic Random-Access Memory，是DDR内存的一种升级版本，相比于DDR和DDR2，它提供了更高的数据传输速度和更低的功耗。DDR3的主要特点包括： 1. **数据传输速率**：DDR3内存的数据传输速率通常从800MT/s到1600MT/s不等，高于DDR2的667MT/s至1066MT/s。在本资源提到的H5TQG83GFR系列中，虽然具体速度未给出，但作为2015年的产品，它们很可能支持1066MT/s到1333MT/s的频率。 2. **电压降低**：DDR3的工作电压比DDR2更低，为1.5V，而DDR2是1.8V，这有助于减少系统的能耗。 3. **Bank Group架构**：DDR3引入了Bank Group架构，可以同时处理多个银行的读写操作，提高了内存访问效率。 4. **预取位宽**：DDR3的预取位宽通常是8位，而DDR2是4位，这意味着DDR3可以在每个时钟周期内处理更多的数据。 5. **时钟同步**：DDR3内存的工作是与系统时钟同步的，数据在时钟的上升沿和下降沿都被传输，从而实现了双倍数据速率。 6. **封装和容量**：H5TQG83GFR系列内存芯片是2GB容量的，采用32片x8或16片x16的组织结构，形成2,147,483,648位（2GB）的总容量。 7. **RoHS合规**：RoHS代表欧盟的《关于限制在电子电气设备中使用某些有害物质的指令》，产品标识中的“Lead-Free&Halogen-Free”表示这些内存芯片不含铅且不含卤素，符合环保要求。 8. **修订历史**：从文档的修订历史可以看出，产品经历了多次更新，包括包尺寸、IDD（电源电流需求）和操作注意事项等方面的改进。 9. **IDD更新**：IDD是指集成电路的静态和动态电源消耗，每次更新可能涉及了对不同工作模式下电流消耗的调整，以优化性能和能效。 10. **操作注意事项**：更新可能包含了对正确使用和安装内存的额外指导，以确保其稳定性和兼容性。 DDR3_H5TQG83GFR是SK海力士生产的高性能、低功耗内存芯片，广泛应用于需要高效能内存的系统中，如服务器、工作站和个人计算机。其设计和制造遵循了严格的行业标准，确保了产品的可靠性和环保特性。

Rev. 1.2 / Oct.2015 7

Pin Functional Description

Symbol Type Function

CK, CK Input

Clock: CK and CK

are differential clock inputs. All address and control input signals are

sampled on the crossing of the positive edge of CK and negative edge of CK

CKE, (CKE0),

(CKE1)

Input

Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and

device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down

and Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any

bank).

CKE is asynchronous for Self-Refresh exit. After VREFCA and VREFDQ have become stable

during the power on and initialization sequence, they must be maintained during all

operations (including Self-Refresh). CKE must be maintained high throughout read and

write accesses. Input buffers, excluding CK, CK

, ODT and CKE, are disabled during power-

down. Input buffers, excluding CKE, are disabled during Self-Refresh.

, (CS0),

(CS

1), (CS2),

(CS

Input

Chip Select: All commands are masked when CS

is registered HIGH.

provides for external Rank selection on systems with multiple Ranks.

is considered part of the command code.

ODT, (ODT0),

(ODT1)

Input

On Die Termination: ODT (registered HIGH) enables termination resistance internal to the

DDR3 SDRAM. When enabled, ODT is only applied to each DQ, DQS, DQS and DM/TDQS,

NU/TDQS

(When TDQS is enabled via Mode Register A11=1 in MR1) signal for x4/x8

configurations. For x16 configuration, ODT is applied to each DQ, DQSU, DQSU

, DQSL,

DQSL

, DMU, and DML signal. The ODT pin will be ignored if MR1 is programmed to disable

ODT.

RAS

CAS

. WE

Input

Command Inputs: RAS

, CAS and WE (along with CS) define the command being entered.

DM, (DMU),

(DML)

Input

Input Data Mask: DM is an input mask signal for write data. Input data is masked when

DM is sampled HIGH coincident with that input data during a Write access. DM is sampled

on both edges of DQS. For x8 device, the function of DM or TDQS/TDQS

is enabled by

Mode Register A11 setting in MR1.

BA0 - BA2

Input

Bank Address Inputs: BA0 - BA2 define to which bank an Active, Read, Write or Precharge

command is being applied. Bank address also determines if the mode register or extended

mode register is to be accessed during a MRS cycle.

A0 - A15

Input

Address Inputs: Provide the row address for Active commands and the column address for

Read/Write commands to select one location out of the memory array in the respective

bank. (A10/AP and A12/BC

have additional functions, see below).

The address inputs also provide the op-code during Mode Register Set commands.

A10 / AP

Input

Auto-precharge: A10 is sampled during Read/Write commands to determine whether

Autoprecharge should be performed to the accessed bank after the Read/Write operation.

(HIGH: Autoprecharge; LOW: no Autoprecharge).A10 is sampled during a Precharge

command to determine whether the Precharge applies to one bank (A10 LOW) or all

banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by bank

addresses.

A12 / BC

Input

Burst Chop: A12 / BC

is sampled during Read and Write commands to determine if burst

chop (on-the-fly) will be performed.

(HIGH, no burst chop; LOW: burst chopped). See command truth table for details.

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