TI-TCA9548A-Q1: 汽车级8通道I2C开关与功能安全设计

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TI-TCA9548A-Q1是一款专为汽车应用设计的高性能I2C开关，它符合AEC-Q100等级1标准，确保在严苛的汽车环境中稳定运行。该芯片提供了八路双向转换开关，每个通道均可通过I2C总线独立控制，允许灵活的I2C地址映射，解决多路设备共享同一地址的问题，例如在连接多个相同数字温度传感器时。其主要特性包括： 1. 功能安全：提供详细的文档支持，帮助设计者构建安全可靠的功能系统。 2. 低电平有效的复位输入：当系统控制器检测到故障时，可通过复位信号轻松重启TCA9548A-Q1，无需中断供电。 3. 多种电压兼容性：支持1.8V、2.5V、3.3V和5V电压等级间的切换，允许不同电压的设备间通信。 4. 热插拔和低静态电流：设计考虑了实时操作的灵活性，同时保持较低的能耗。 5. 宽广的工作电源电压范围：1.65V至5.25V，适应各种供电环境。 6. 低阻抗开关：RON值低，有助于减少信号传输损耗。 7. 高速接口：支持400kHz的时钟频率，满足高速数据传输需求。 8. 闩锁性能：超过100mA的电流处理能力，符合JESD78II类规范，保证信号完整性。在应用方面，TCA9548A-Q1广泛用于信息娱乐系统、车身控制、电信交换设备（如路由器）、工厂自动化以及存在I2C地址冲突的场景，如多个温度传感器。使用时，用户可以通过编程寄存器来配置各个通道的开关状态，上电时默认所有通道关闭。器件的VCC引脚用于限制最高电压传输，外部上拉电阻则用于调整各通道的电压水平，使其与不同的设备兼容。所有I/O引脚能承受高达5V的电压，确保信号完整性。 TCA9548A-Q1的封装形式为VQFN(24)，尺寸为4.00mm×4.00mm，如需了解更多封装选项，请查阅数据表中的可订购产品附录。这款I2C开关是汽车电子系统中不可或缺的组件，提供了高效、可靠和灵活的I2C扩展解决方案。

6.5 Electrical Characteristics

(1)

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS V

MIN TYP MAX UNIT

PORR

Power-on reset voltage, V

rising No load, V

= V

or GND

(4)

1.2 1.5 V

PORF

Power-on reset voltage, V

falling

(2)

No load, V

= V

or GND

(4)

0.8 1 V

o(sw)

Switch output voltage

i(sw)

= V

, I

SWout

= –100 μA

5 V 3.6

4.5 V to 5.25 V 2.6 4.5

3.3 V 1.9

3 V to 3.6 V 1.6 2.8

2.5 V 1.5

2.3 V to 2.7 V 1.1 2

1.8 V 1.1

1.65 V to 1.95 V 0.6 1.25

SDA

= 0.4 V

1.65 V to 5.25 V

3 6

= 0.6 V 5 9

SCL, SDA

= V

or GND

(4)

1.65 V to 5.25 V

–1

μA

SC7–SC0, SD7–SD0 –1

A2–A0 –1

RESET

–1

Operating mode

SCL

= 400 kHz V

= V

or GND

(4)

, I

= 0

5.25 V 50 80

μA

3.6 V 20 35

2.7 V 11 20

1.65 V 6 10

SCL

= 100 kHz V

= V

or GND

(4)

, I

= 0

5.25 V 9 30

3.6 V 6 15

2.7 V 4 8

1.65 V 2 4

Standby mode

Low inputs V

= GND

(4)

, I

= 0

5.25 V 0.2 4

3.6 V 0.1 2

2.7 V 0.1 2

1.65 V 0.1 1

High inputs V

= V

, I

= 0

5.25 V 0.2 4

3.6 V 0.1 2

2.7 V 0.1 2

1.65 V 0.1 1

ΔI

Supply-current

change

SCL, SDA

SCL or SDA input at 0.6 V,

Other inputs at V

or GND

(4)

1.65 V to 5.25 V

3 20

μA

SCL or SDA input at V

– 0.6 V,

Other inputs at V

or GND

(4)

3 20

A2–A0

= V

or GND

(4)

1.65 V to 5.25 V

4 5

RESET 4 5

SCL V

= V

or GND

(4)

, Switch OFF 20 28

io(off)

(3)

SDA

= V

or GND

(4)

, Switch OFF 1.65 V to 5.25 V

20 28

SC7–SC0, SD7–SD0

5.5 7.5

Switch-on resistance

= 0.4 V, I

= 15 mA

4.5 V to 5.25 V 4 10 25

Ω

3 V to 3.6 V 5 12 35

= 0.4 V, I

= 10 mA

2.3 V to 2.7 V 7 15 45

1.65 V to 1.95 V 10 25 70

(1) For operation between specified voltage ranges, refer to the worst-case parameter in both applicable ranges.

(2) The power-on reset circuit resets the I

C bus logic with V

< V

PORF

(3) C

io(ON)

depends on internal capacitance and external capacitance added to the SCn lines when channels(s) are ON.

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TCA9548A-Q1

ZHCSJQ8B – MAY 2019 – REVISED OCTOBER 2021

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(4) RESET = V

(held high) when all other input voltages, V

= GND.

6.6 I

C Interface Timing Requirements

over recommended operating free-air temperature range (unless otherwise noted) (see 图 7-1)

MIN MAX UNIT

STANDARD MODE

scl

C clock frequency 0 100 kHz

sch

C clock high time 4

μs

scl

C clock low time 4.7

μs

C spike time 50 ns

sds

C serial-data setup time 250 ns

sdh

C serial-data hold time 0

(1)

μs

icr

C input rise time 1000 ns

icf

C input fall time 300 ns

ocf

C output (SDn) fall time (10 pF to 400 pF bus) 300 ns

buf

C bus free time between stop and start 4.7

μs

sts

C start or repeated start condition setup 4.7

μs

sth

C start or repeated start condition hold 4

μs

sps

C stop condition setup 4

μs

vdL(Data)

Valid-data time (high to low)

(2)

SCL low to SDA output low valid 1

μs

vdH(Data)

Valid-data time (low to high)

(2)

SCL low to SDA output high valid 0.6

μs

vd(ack)

Valid-data time of ACK condition

ACK signal from SCL low

to SDA output low

μs

C bus capacitive load 400 pF

FAST MODE

scl

C clock frequency 0 400 kHz

sch

C clock high time 0.6

μs

scl

C clock low time 1.3

μs

C spike time 50 ns

sds

C serial-data setup time 100 ns

sdh

C serial-data hold time 0

(1)

μs

icr

C input rise time 20 300 ns

icf

C input fall time

20 × (V

5.5 V)

300 ns

ocf

C output (SDn) fall time (10 pF to 400 pF bus)

20 × (V

5.5 V)

300 ns

buf

C bus free time between stop and start 1.3

μs

sts

C start or repeated start condition setup 0.6

μs

sth

C start or repeated start condition hold 0.6

μs

sps

C stop condition setup 0.6

μs

vdL(Data)

Valid-data time (high to low)

(2)

SCL low to SDA output low valid 1

μs

vdH(Data)

Valid-data time (low to high)

(2)

SCL low to SDA output high valid 0.6

μs

vd(ack)

Valid-data time of ACK condition

ACK signal from SCL low

to SDA output low

μs

C bus capacitive load 400 pF

(1) A device internally must provide a hold time of at least 300 ns for the SDA signal (referred to the V

min of the SCL signal), to bridge

the undefined region of the falling edge of SCL.

(2) Data taken using a 1 kΩ pull-up resistor and 50 pF load (see 图 7-2)

TCA9548A-Q1

ZHCSJQ8B – MAY 2019 – REVISED OCTOBER 2021

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