![](https://csdnimg.cn/release/download_crawler_static/87429369/bg6.jpg)
(4) RESET = V
CC
(held high) when all other input voltages, V
I
= GND.
6.6 I
2
C Interface Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see 图 7-1)
MIN MAX UNIT
STANDARD MODE
f
scl
I
2
C clock frequency 0 100 kHz
t
sch
I
2
C clock high time 4
μs
t
scl
I
2
C clock low time 4.7
μs
t
sp
I
2
C spike time 50 ns
t
sds
I
2
C serial-data setup time 250 ns
t
sdh
I
2
C serial-data hold time 0
(1)
μs
t
icr
I
2
C input rise time 1000 ns
t
icf
I
2
C input fall time 300 ns
t
ocf
I
2
C output (SDn) fall time (10 pF to 400 pF bus) 300 ns
t
buf
I
2
C bus free time between stop and start 4.7
μs
t
sts
I
2
C start or repeated start condition setup 4.7
μs
t
sth
I
2
C start or repeated start condition hold 4
μs
t
sps
I
2
C stop condition setup 4
μs
t
vdL(Data)
Valid-data time (high to low)
(2)
SCL low to SDA output low valid 1
μs
t
vdH(Data)
Valid-data time (low to high)
(2)
SCL low to SDA output high valid 0.6
μs
t
vd(ack)
Valid-data time of ACK condition
ACK signal from SCL low
to SDA output low
1
μs
C
b
I
2
C bus capacitive load 400 pF
FAST MODE
f
scl
I
2
C clock frequency 0 400 kHz
t
sch
I
2
C clock high time 0.6
μs
t
scl
I
2
C clock low time 1.3
μs
t
sp
I
2
C spike time 50 ns
t
sds
I
2
C serial-data setup time 100 ns
t
sdh
I
2
C serial-data hold time 0
(1)
μs
t
icr
I
2
C input rise time 20 300 ns
t
icf
I
2
C input fall time
20 × (V
CC
/
5.5 V)
300 ns
t
ocf
I
2
C output (SDn) fall time (10 pF to 400 pF bus)
20 × (V
CC
/
5.5 V)
300 ns
t
buf
I
2
C bus free time between stop and start 1.3
μs
t
sts
I
2
C start or repeated start condition setup 0.6
μs
t
sth
I
2
C start or repeated start condition hold 0.6
μs
t
sps
I
2
C stop condition setup 0.6
μs
t
vdL(Data)
Valid-data time (high to low)
(2)
SCL low to SDA output low valid 1
μs
t
vdH(Data)
Valid-data time (low to high)
(2)
SCL low to SDA output high valid 0.6
μs
t
vd(ack)
Valid-data time of ACK condition
ACK signal from SCL low
to SDA output low
1
μs
C
b
I
2
C bus capacitive load 400 pF
(1) A device internally must provide a hold time of at least 300 ns for the SDA signal (referred to the V
IH
min of the SCL signal), to bridge
the undefined region of the falling edge of SCL.
(2) Data taken using a 1 kΩ pull-up resistor and 50 pF load (see 图 7-2)
TCA9548A-Q1
ZHCSJQ8B – MAY 2019 – REVISED OCTOBER 2021
www.ti.com.cn
6 Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TCA9548A-Q1