LPC214x用户手册：ARM单片机USB开发关键指南

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"LPC214x用户手册是针对基于ARM7内核的LPC2148、LPC2146等芯片的详细开发指南，涵盖了32位微控制器、USB2.0设备接口等相关知识。" 该手册详细介绍了NXP半导体公司生产的LPC214x系列微控制器，这是一系列基于高效能ARM7TDMI-S内核的单片机，适用于嵌入式应用。手册包含了关于LPC2141、LPC2142、LPC2144、LPC2146和LPC2148型号的具体信息，这些芯片具备丰富的外设接口，如USB2.0设备端口，使得它们在开发USB相关的项目中尤其有用。手册的修订历史显示，文档经过多次更新以提供最新的信息和技术改进。例如，第4版中增加了设备修订寄存器（Section21.8.11），并指出为了访问USBSRAM，必须设置PCONP寄存器中的PCUSB位（Table31）。此外，还修正了I2C章节的多个错误（Chapter14“LPC214x I2C总线接口I2C0/1”），更新了IAP（In-Application Programming）调用示例（Section21.9），以及更新了看门狗Feed寄存器（WDFEED，Section16.4.3）的描述。 LPC214x系列的特点包括： 1. **ARM7TDMI-S内核**：32位RISC架构，提供了高性能计算能力。 2. **USB2.0支持**：内置USB设备控制器，支持高速和全速操作，方便开发USB相关产品。 3. **多种内存接口**：包括SRAM、Flash存储器，以及可能的外部存储器接口，便于扩展存储需求。 4. **丰富的外设集**：如I2C、SPI、UART、PWM、ADC、DAC等，满足多样化应用需求。 5. **IAP功能**：允许在应用中进行程序更新和维护，增强了系统灵活性。 6. **电源管理**：通过PCONP寄存器控制各模块电源，优化功耗。对于开发者而言，LPC214x用户手册是深入理解和开发基于这些芯片的项目的宝贵资源。它提供了详细的硬件描述、寄存器配置、编程模型、中断处理、调试技巧以及故障排查方法。通过深入阅读和理解这份手册，开发者可以充分利用LPC214x系列的优势，实现高效、可靠的嵌入式系统设计。

User manual Rev. 4 — 23 April 2012 16 of 354

3.1 Introduction

The MAM block in the LPC2141/2/4/6/8 maximizes the performance of the ARM

processor when it is running code in Flash memory, but does so using a single Flash

bank.

3.2 Operation

Simply put, the Memory Accelerator Module (MAM) attempts to have the next ARM

instruction that will be needed in its latches in time to prevent CPU fetch stalls. The

LPC2141/2/4/6/8 uses one bank of Flash memory, compared to the two banks used on

predecessor devices. It includes three 128-bit buffers called the Prefetch Buffer, the

Branch Trail Buffer and the data buffer. When an Instruction Fetch is not satisfied by either

the Prefetch or Branch Trail Buffer, nor has a prefetch been initiated for that line, the ARM

is stalled while a fetch is initiated for the 128-bit line. If a prefetch has been initiated but not

yet completed, the ARM is stalled for a shorter time. Unless aborted by a data access, a

prefetch is initiated as soon as the Flash has completed the previous access. The

prefetched line is latched by the Flash module, but the MAM does not capture the line in

its prefetch buffer until the ARM core presents the address from which the prefetch has

been made. If the core presents a different address from the one from which the prefetch

has been made, the prefetched line is discarded.

The Prefetch and Branch Trail buffers each include four 32-bit ARM instructions or eight

16-bit Thumb instructions. During sequential code execution, typically the Prefetch Buffer

contains the current instruction and the entire Flash line that contains it.

The MAM differentiates between instruction and data accesses. Code and data accesses

use separate 128-bit buffers. 3 of every 4 sequential 32-bit code or data accesses "hit" in

the buffer without requiring a Flash access (7 of 8 sequential 16-bit accesses, 15 of every

16 sequential byte accesses). The fourth (eighth, 16th) sequential data access must

access Flash, aborting any prefetch in progress. When a Flash data access is concluded,

any prefetch that had been in progress is re-initiated.

Timing of Flash read operations is programmable and is described later in this section.

In this manner, there is no code fetch penalty for sequential instruction execution when the

CPU clock period is greater than or equal to one fourth of the Flash access time. The

average amount of time spent doing program branches is relatively small (less than 25%)

and may be minimized in ARM (rather than Thumb) code through the use of the

conditional execution feature present in all ARM instructions. This conditional execution

may often be used to avoid small forward branches that would otherwise be necessary.

Branches and other program flow changes cause a break in the sequential flow of

instruction fetches described above. The Branch Trail Buffer captures the line to which

such a non-sequential break occurs. If the same branch is taken again, the next

instruction is taken from the Branch Trail Buffer. When a branch outside the contents of

UM10139

Chapter 3: LPC214x Memory accelerator module

Rev. 4 — 23 April 2012 User manual

User manual Rev. 4 — 23 April 2012 18 of 354

NXP Semiconductors

UM10139

Chapter 3: LPC214x Memory accelerator module

3.3.2 Instruction latches and data latches

Code and Data accesses are treated separately by the Memory Accelerator Module.

There is a 128-bit Latch, a 15-bit Address

Latch, and a 15-bit comparator associated with each buffer (prefetch, branch trail, and

data). Each 128-bit latch holds 4 words (4 ARM instructions, or 8 Thumb instructions).

Also associated with each buffer are 32 4:1 Multiplexers that select the requested word

from the 128-bit line.

Each Data access that is not in the Data latch causes a Flash fetch of 4 words of data,

which are captured in the Data latch. This speeds up sequential Data operations, but has

little or no effect on random accesses.

3.3.3 Flash programming issues

Since the Flash memory does not allow accesses during programming and erase

operations, it is necessary for the MAM to force the CPU to wait if a memory access to a

Flash address is requested while the Flash module is busy. (This is accomplished by

asserting the ARM7TDMI-S local bus signal CLKEN.) Under some conditions, this delay

could result in a Watchdog time-out. The user will need to be aware of this possibility and

take steps to insure that an unwanted Watchdog reset does not cause a system failure

while programming or erasing the Flash memory.

In order to preclude the possibility of stale data being read from the Flash memory, the

LPC2141/2/4/6/8 MAM holding latches are automatically invalidated at the beginning of

any Flash programming or erase operation. Any subsequent read from a Flash address

will cause a new fetch to be initiated after the Flash operation has completed.

3.4 MAM operating modes

Three modes of operation are defined for the MAM, trading off performance for ease of

predictability:

Mode 0: MAM off. All memory requests result in a Flash read operation (see note 2

below). There are no instruction prefetches.

Mode 1: MAM partially enabled. Sequential instruction accesses are fulfilled from the

holding latches if the data is present. Instruction prefetch is enabled. Non-sequential

instruction accesses initiate Flash read operations (see note 2 below). This means that

all branches cause memory fetches. All data operations cause a Flash read because

buffered data access timing is hard to predict and is very situation dependent.

Mode 2: MAM fully enabled. Any memory request (code or data) for a value that is

contained in one of the corresponding holding latches is fulfilled from the latch.

Instruction prefetch is enabled. Flash read operations are initiated for instruction

prefetch and code or data values not available in the corresponding holding latches.

User manual Rev. 4 — 23 April 2012 19 of 354

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UM10139

Chapter 3: LPC214x Memory accelerator module

[1] Instruction prefetch is enabled in modes 1 and 2.

[2] The MAM actually uses latched data if it is available, but mimics the timing of a Flash read operation. This

saves power while resulting in the same execution timing. The MAM can truly be turned off by setting the

fetch timing value in MAMTIM to one clock.

[1] The MAM actually uses latched data if it is available, but mimics the timing of a Flash read operation. This

saves power while resulting in the same execution timing. The MAM can truly be turned off by setting the

fetch timing value in MAMTIM to one clock.

3.5 MAM configuration

After reset the MAM defaults to the disabled state. Software can turn memory access

acceleration on or off at any time. This allows most of an application to be run at the

highest possible performance, while certain functions can be run at a somewhat slower

but more predictable rate if more precise timing is required.

3.6 Register description

All registers, regardless of size, are on word address boundaries. Details of the registers

appear in the description of each function.

Table 5. MAM responses to program accesses of various types

Program Memory Request Type MAM Mode

0 1 2

Sequential access, data in latches Initiate Fetch

[2]

Use Latched

Data

[1]

Use Latched

Data

[1]

Sequential access, data not in latches Initiate Fetch Initiate Fetch

[1]

Initiate Fetch

[1]

Non-sequential access, data in latches Initiate Fetch

[2]

Initiate Fetch

[1][2]

Use Latched

Data

[1]

Non-sequential access, data not in latches Initiate Fetch Initiate Fetch

[1]

Initiate Fetch

[1]

Table 6. MAM responses to data and DMA accesses of various types

Data Memory Request Type MAM Mode

0 1 2

Sequential access, data in latches Initiate Fetch

[1]

Initiate Fetch

[1]

Use Latched

Data

Sequential access, data not in latches Initiate Fetch Initiate Fetch Initiate Fetch

Non-sequential access, data in latches Initiate Fetch

[1]

Initiate Fetch

[1]

Use Latched

Data

Non-sequential access, data not in latches Initiate Fetch Initiate Fetch Initiate Fetch

User manual Rev. 4 — 23 April 2012 20 of 354

NXP Semiconductors

UM10139

Chapter 3: LPC214x Memory accelerator module

[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.

3.7 MAM Control Register (MAMCR - 0xE01F C000)

Two configuration bits select the three MAM operating modes, as shown in Table 8.

Following Reset, MAM functions are disabled. Changing the MAM operating mode causes

the MAM to invalidate all of the holding latches, resulting in new reads of Flash

information as required.

3.8 MAM Timing register (MAMTIM - 0xE01F C004)

The MAM Timing register determines how many CCLK cycles are used to access the

Flash memory. This allows tuning MAM timing to match the processor operating

frequency. Flash access times from 1 clock to 7 clocks are possible. Single clock Flash

accesses would essentially remove the MAM from timing calculations. In this case the

MAM mode may be selected to optimize power usage.

Table 7. Summary of MAM registers

Name Description Access Reset

value

[1]

Address

MAMCR Memory Accelerator Module Control Register.

Determines the MAM functional mode, that is, to

what extent the MAM performance enhancements

are enabled. See Table 8

R/W 0x0 0xE01F C000

MAMTIM Memory Accelerator Module Timing control.

Determines the number of clocks used for Flash

memory fetches (1 to 7 processor clocks).

R/W 0x07 0xE01F C004

Table 8. MAM Control Register (MAMCR - address 0xE01F C000) bit description

Bit Symbol Value Description Reset

value

1:0 MAM_mode

_control

00 MAM functions disabled 0

01 MAM functions partially enabled

10 MAM functions fully enabled

11 Reserved. Not to be used in the application.

7:2 - - Reserved, user software should not write ones to reserved

bits. The value read from a reserved bit is not defined.

Table 9. MAM Timing register (MAMTIM - address 0xE01F C004) bit description

Bit Symbol Value Description Reset

value

2:0 MAM_fetch_

cycle_timing

000 0 - Reserved. 07

001 1 - MAM fetch cycles are 1 processor clock (CCLK) in

duration

010 2 - MAM fetch cycles are 2 CCLKs in duration

011 3 - MAM fetch cycles are 3 CCLKs in duration

100 4 - MAM fetch cycles are 4 CCLKs in duration

101 5 - MAM fetch cycles are 5 CCLKs in duration

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