4 Volume I: RISC-V Unprivileged ISA V20181221-Public-Review-draft
An execution environment implementation might time-multiplex a set of guest harts onto
fewer host harts provided by its own execution environment but must do so in a way that guest
harts operate like independent hardware threads. In particular, if there are more guest harts than
host harts then the execution environment must be able to preempt the guest harts and must not
wait indefinitely for guest software on a guest hart to ”yield” control of the guest hart.
1.3 RISC-V ISA Overview
A RISC-V ISA is defined as a base integer ISA, which must be present in any implementation, plus
optional extensions to the base ISA. The base integer ISAs are very similar to that of the early
RISC processors except with no branch delay slots and with support for optional variable-length
instruction encodings. A base is carefully restricted to a minimal set of instructions sufficient to
provide a reasonable target for compilers, assemblers, linkers, and operating systems (with addi-
tional privileged operations), and so provides a convenient ISA and software toolchain “skeleton”
around which more customized processor ISAs can be built.
Although it is convenient to speak of the RISC-V ISA, RISC-V is actually a family of related ISAs,
of which there are currently four base ISAs. Each base integer instruction set is characterized by
the width of the integer registers and the corresponding size of the address space and by the number
of integer registers. There are two primary base integer variants, RV32I and RV64I, described in
Chapters 2 and 5, which provide 32-bit or 64-bit address spaces respectively. We use the term
XLEN to refer to the width of an integer register in bits (either 32 or 64). Chapter 4 describes
the RV32E subset variant of the RV32I base instruction set, which has been added to support
small microcontrollers, and which has half the number of integer registers. Chapter 6 sketches a
future RV128I variant of the base integer instruction set supporting a flat 128-bit address space
(XLEN=128). The base integer instruction sets use a two’s-complement representation for signed
integer values.
Although 64-bit address spaces are a requirement for larger systems, we believe 32-bit address
spaces will remain adequate for many embedded and client devices for decades to come and will
be desirable to lower memory traffic and energy consumption. In addition, 32-bit address spaces
are sufficient for educational purposes. A larger flat 128-bit address space might eventually be
required, so we ensured this could be accommodated within the RISC-V ISA framework.
The four base ISAs in RISC-V are treated as distinct base ISAs. A common question is why
is there not a single ISA, and in particular, why is RV32I not a strict subset of RV64I? Some
earlier ISA designs (SPARC, MIPS) adopted a strict superset policy when increasing address
space size to support running existing 32-bit binaries on new 64-bit hardware.
The main advantage of explicitly separating base ISAs is that each base ISA can be opti-
mized for its needs without requiring to support all the operations needed for other base ISAs.
For example, RV64I can omit instructions and CSRs that are only needed to cope with the nar-
rower registers in RV32I. The RV32I variants can use encoding space otherwise reserved for
instructions only required by wider address-space variants.
The main disadvantage of not treating the design as a single ISA is that it complicates
the hardware needed to emulate one base ISA on another (e.g., RV32I on RV64I). However,
differences in addressing and illegal instruction traps generally mean some mode switch would
be required in hardware in any case even with full superset instruction encodings, and the different
RISC-V base ISAs are similar enough that supporting multiple versions is relatively low cost.
Although some have proposed that the strict superset design would allow legacy 32-bit libraries