中国大学生电子设计竞赛获奖论文：7476系列双主从JK触发器芯片资料

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"该文档是关于中国电子设计竞赛中的一篇获奖论文，主要讨论了7476系列芯片，具体型号为5476/DM5476/DM7476的双主从JK触发器。这些触发器具有清除(Clear)、预置(Preset)和互补输出功能，适用于大学生在设计竞赛中作为芯片资料和方案参考。 7476系列是一种集成电路，包含两个独立的、正脉冲触发的JK触发器，每个触发器都有自己的输出。数据在时钟信号完整周期后进行处理，当时钟信号低时，主从触发器相互隔离。在时钟上升沿，来自J和K输入的数据会被传输到主触发器，而当时钟为高电平时，J和K输入被禁用，防止逻辑状态改变。数据实际传输发生在时钟下降沿，这确保了操作的稳定性。重要特性包括提供军事和航空应用的备用版本5476，这可能具有更高的可靠性和适应性。为了获取更多详细信息，用户需要联系国家半导体销售办公室或分销商，以了解产品的规格、性能以及可能的使用限制和应用指导。这篇论文对于参赛者来说，不仅提供了技术原理的深入理解，还可能包含了设计方法、电路实现策略以及如何优化性能以满足竞赛需求等实用知识。对于电子工程专业的学生来说，这是一份宝贵的参考资料，可以帮助他们在竞赛中脱颖而出，提高他们的设计能力和实践经验。"

TL/F/6528

5476/DM5476/DM7476 Dual Master-Slave J-K Flip-Flops

with Clear, Preset, and Complementary Outputs

June 1989

5476/DM5476/DM7476

Dual Master-Slave J-K Flip-Flops with Clear,

Preset, and Complementary Outputs

General Description

This device contains two independent positive pulse trig-

gered J-K flip-flops with complementary outputs. The J and

K data is processed by the flip-flop after a complete clock

pulse. While the clock is low the slave is isolated from the

master. On the positive transition of the clock, the data from

the J and K inputs is transferred to the master. While the

clock is high the J and K inputs are disabled. On the nega-

tive transition of the clock, the data from the master is trans-

ferred to the slave. The logic state of J and K inputs must

not be allowed to change while the clock is high. The data is

transfered to the outputs on the falling edge of the clock

pulse. A low logic level on the preset or clear inputs will set

or reset the outputs regardless of the logic levels of the

other inputs.

Features

Alternate Military/Aerospace device (5476) is available.

Contact a National Semiconductor Sales Office/Distrib-

utor for specifications.

Connection Diagram

Dual-In-Line Package

TL/F/6528–1

Order Number 5476DMQB, 5476FMQB,

DM5476J, DM5476W or DM7476N

See NS Package Number J16A, N16E or W16A

Function Table

Inputs Outputs

PR CLR CLK J K Q Q

LH XXXHL

HL XXXLH

LL XXXH*H*

HHÉLLQ

HHÉHL H L

HHÉLH L H

HHÉH H Toggle

High Logic Level

Low Logic Level

Either Low or High Logic Level

Positive pulse data. The J and K inputs must be held constant while

the clock is high. Data is transfered to the outputs on the falling edge of the

clock pulse.

This configuration is nonstable; that is, it will not persist when the preset

and/or clear inputs return to their inactive (high) level.

The output logic level before the indicated input conditions were es-

tablished.

Toggle

Each output changes to the complement of its previous level on

each complete active high level clock pulse.

1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

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