Micron Mobile Low-Power DDR SDRAM技术规格

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Micron-MT46H16M32LFB5-6 ATC.pdf 是一份关于Micron公司生产的Mobile Low-Power DDR SDRAM（移动低功耗双倍数据速率同步动态随机存取存储器）的数据手册，主要介绍了MT46H系列的三种不同型号：MT46H32M16LF-8、MT46H16M32LF-4和MT46H16M32LG-4。这些内存芯片主要用于需要低功耗和高效能的移动设备中。关键知识点： 1. **电压范围**：这些器件工作在1.70V到1.95V的电压范围内，这是为了降低功耗，适应移动设备的需求。 2. **双向数据 strobe（DQS）**：每个数据字节都有一个独立的双向数据 strobe，它与数据同步，用于读写操作的精确时序控制。 3. **内部流水线双倍数据速率（DDR）架构**：每个时钟周期可以执行两次数据访问，一次在时钟上升沿，一次在下降沿，显著提高了数据传输速率。 4. **差分时钟输入**：使用CK和CK#（时钟和反相时钟）差分信号，可以提高信号质量，降低干扰。 5. **命令输入**：命令在每个正向CK边缘进入，确保了指令的及时执行。 6. **数据对齐**：在读取操作中，DQS信号与数据边缘对齐；在写入操作中，DQS信号与数据居中对齐，确保数据传输的准确性。 7. **4个内部银行**：支持并发操作，提高了内存的并行处理能力。 8. **数据掩码（DM）**：提供数据写入掩码功能，每字节一个掩码，用于控制写入数据。 9. **可编程突发长度（BL）**：支持2、4、8或16的突发长度，提供了灵活性，以适应不同的数据访问模式。 10. **并发自动预充选项**：允许在不中断其他操作的情况下进行预充，提高了内存效率。 11. **自动刷新和自刷新模式**：自动刷新确保数据完整性，自刷新模式则在系统待机时保持内存状态。 12. **1.8V LVC MOS兼容输入**：采用1.8V低电压互补金属氧化物半导体输入，进一步降低功耗。 13. **温度补偿自刷新（TCSR）**：根据温度变化调整刷新频率，确保在不同环境温度下的稳定工作。 14. **部分数组自刷新（PASR）**：允许只刷新部分内存阵列，节省更多功耗。 15. **深度电源下拉（DPD）**：在设备不活动时，可以进入低功耗模式。 16. **状态读寄存器（SRR）**：提供读取设备状态的能力。 17. **可选的输出驱动强度（DS）**：允许用户根据需求调整输出驱动强度。 18. **时钟停止能力**：在不需要时可以停止时钟，进一步降低功耗。 19. **刷新周期**：64毫秒刷新周期，针对汽车温度环境，也有32毫秒的刷新周期选项，以满足严格的车载电子设备要求。表格1列出了不同速度等级的关键时序参数，例如-5、-54、-6和-75，它们对应不同的时钟速率和访问时间，显示了这些内存芯片在不同工作条件下的性能表现。

Figure 7: 90-Ball VFBGA (8mm x 13mm), Package Code: B5

Seating plane

0.12 A

Ball A1 ID

0.275 MIN

0.9 ±0.1

6.4 CTR

8 ±0.1

0.8 TYP

13 ±0.1

0.8 TYP

11.2 CTR

90X Ø0.45

Dimensions apply to

solder balls post-reflow

on Ø0.40 SMD ball pads.

Solder ball material:

SAC305 (96.5% Sn, 3% Ag,

0.5% Cu) OR

SAC105 (98.5% Sn, 1% Ag,

0.5% Cu).

Ball A1 ID

(covered by SR)

123789

Note:

1. All dimensions are in millimeters.

512Mb: x16, x32 Mobile LPDDR SDRAM

Package Dimensions

PDF: 09005aef83dd2b3e

t67m_512mb_mobile_lpddr.pdf - Rev. I 01/14 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Electrical Specifications

Stresses greater than those listed may cause permanent damage to the device. This is a

stress rating only, and functional operation of the device at these or any other condi-

tions above those indicated in the operational sections of this specification is not im-

plied. Exposure to absolute maximum rating conditions for extended periods may affect

reliability.

Table 4: Absolute Maximum Ratings

Note 1 applies to all parameters in this table

Parameter Symbol Min Max Unit

DDQ

supply voltage relative to V

DDQ

–1.0 2.4 V

Voltage on any pin relative to V

–0.5 2.4 or (V

DDQ

+ 0.3V),

whichever is less

Storage temperature (plastic) T

STG

–55 150 ˚C

Note:

1. V

and V

DDQ

must be within 300mV of each other at all times. V

DDQ

must not exceed

Table 5: AC/DC Electrical Characteristics and Operating Conditions

Notes 1–5 apply to all parameters/conditions in this table; V

DDQ

= 1.70–1.95V

Parameter/Condition Symbol Min Max Unit Notes

Supply voltage V

1.70 1.95 V 6, 7

I/O supply voltage V

DDQ

1.70 1.95 V 6, 7

Address and command inputs

Input voltage high V

0.8 × V

DDQ

+ 0.3 V 8, 9

Input voltage low V

–0.3 0.2 × V

DDQ

V 8, 9

Clock inputs (CK, CK#)

DC input voltage V

–0.3 V

DDQ

+ 0.3 V 10

DC input differential voltage V

ID(DC)

0.4 × V

DDQ

+ 0.6 V 10, 11

AC input differential voltage V

ID(AC)

0.6 × V

DDQ

+ 0.6 V 10, 11

AC differential crossing voltage V

0.4 × V

DDQ

0.6 × V

DDQ

V 10, 12

Data inputs

DC input high voltage V

IH(DC)

0.7 × V

DDQ

+ 0.3 V 8, 9, 13

DC input low voltage V

IL(DC)

–0.3 0.3 × V

DDQ

V 8, 9, 13

AC input high voltage V

IH(AC)

0.8 × V

DDQ

+ 0.3 V 8, 9, 13

AC input low voltage V

IL(AC)

–0.3 0.2 × V

DDQ

V 8, 9, 13

Data outputs

DC output high voltage: Logic 1 (I

= –0.1mA) V

0.9 × V

DDQ

–V

DC output low voltage: Logic 0 (I

= 0.1mA) V

– 0.1 × V

DDQ

Leakage current

Input leakage current

Any input 0V ≤ V

≤ V

(All other pins not under test = 0V)

–1 1 μA

512Mb: x16, x32 Mobile LPDDR SDRAM

Electrical Specifications

PDF: 09005aef83dd2b3e

t67m_512mb_mobile_lpddr.pdf - Rev. I 01/14 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 5: AC/DC Electrical Characteristics and Operating Conditions (Continued)

Notes 1–5 apply to all parameters/conditions in this table; V

DDQ

= 1.70–1.95V

Parameter/Condition Symbol Min Max Unit Notes

Output leakage current

(DQ are disabled; 0V ≤ V

OUT

≤ V

DDQ

)

–5 5 μA

Operating temperature

Commercial T

0 +70 ˚C

Industrial T

–40 +85 ˚C

Automotive T

–40 +105 ˚C

Notes:

1. All voltages referenced to V

2. All parameters assume proper device initialization.

3. Tests for AC timing, I

, and electrical AC and DC characteristics may be conducted at

nominal supply voltage levels, but the related specifications and device operation are

guaranteed for the full voltage range specified.

4. Outputs measured with equivalent load; transmission line delay is assumed to be very

small:

I/O

20pF

I/O

10pF

Full drive strength Half drive strength

5. Timing and I

tests may use a V

-to-V

swing of up to 1.5V in the test environment,

but input timing is still referenced to V

DDQ

/2 (or to the crossing point for CK/CK#). The

output timing reference voltage level is V

DDQ

/2.

6. Any positive glitch must be less than one-third of the clock cycle and not more than

+200mV or 2.0V, whichever is less. Any negative glitch must be less than one-third of the

clock cycle and not exceed either –150mV or +1.6V, whichever is more positive.

7. V

and V

DDQ

must track each other and V

DDQ

must be less than or equal to V

8. To maintain a valid level, the transitioning edge of the input must:

8a. Sustain a constant slew rate from the current AC level through to the target AC lev-

el, V

IL(AC)

Or V

IH(AC)

8b. Reach at least the target AC level.

8c. After the AC target level is reached, continue to maintain at least the target DC lev-

el, V

IL(DC)

or V

IH(DC)

9. V

overshoot: V

IHmax

= V

DDQ

+ 1.0V for a pulse width ≤3ns and the pulse width cannot

be greater than one-third of the cycle rate. V

undershoot: V

ILmin

= –1.0V for a pulse

width ≤3ns and the pulse width cannot be greater than one-third of the cycle rate.

10. CK and CK# input slew rate must be ≥1 V/ns (2 V/ns if measured differentially).

11. V

is the magnitude of the difference between the input level on CK and the input lev-

el on CK#.

12. The value of V

is expected to equal V

DDQ/2

of the transmitting device and must track

variations in the DC level of the same.

13. DQ and DM input slew rates must not deviate from DQS by more than 10%. 50ps must

be added to

DS and

DH for each 100 mV/ns reduction in slew rate. If slew rate exceeds

4 V/ns, functionality is uncertain.

512Mb: x16, x32 Mobile LPDDR SDRAM

Electrical Specifications

PDF: 09005aef83dd2b3e

t67m_512mb_mobile_lpddr.pdf - Rev. I 01/14 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Electrical Specifications – I

Parameters

Table 7: I

Specifications and Conditions, –40°C to +85°C (x16)

Notes 1–5 apply to all the parameters/conditions in this table; V

DDQ

= 1.70–1.95V

Parameter/Condition Symbol

Max

Unit Notes-5 -54 -6 -75

Operating 1 bank active precharge current:

RC =

RC (MIN);

CK (MIN); CKE is HIGH; CS is HIGH between valid commands;

Address inputs are switching every 2 clock cycles; Data bus in-

puts are stable

DD0

70 65 60 50 mA 6

Precharge power-down standby current: All banks idle; CKE is

LOW; CS is HIGH;

CK =

CK (MIN); Address and control inputs

are switching; Data bus inputs are stable

DD2P

300 300 300 300 μA 7, 8

Precharge power-down standby current: Clock stopped; All

banks idle; CKE is LOW; CS is HIGH; CK = LOW, CK# = HIGH; Ad-

dress and control inputs are switching; Data bus inputs are sta-

ble

DD2PS

300 300 300 300 μA7

Precharge nonpower-down standby current: All banks idle;

CKE = HIGH; CS = HIGH;

CK =

CK (MIN); Address and control

inputs are switching; Data bus inputs are stable

DD2N

15 15 15 12 mA 9

Precharge nonpower-down standby current: Clock stopped; All

banks idle; CKE = HIGH; CS = HIGH; CK = LOW, CK# = HIGH; Ad-

dress and control inputs are switching; Data bus inputs are sta-

ble

DD2NS

8888mA9

Active power-down standby current: 1 bank active; CKE = LOW;

CS = HIGH;

CK =

CK (MIN); Address and control inputs are

switching; Data bus inputs are stable

DD3P

3333mA8

Active power-down standby current: Clock stopped; 1 bank ac-

tive; CKE = LOW; CS = HIGH; CK = LOW; CK# = HIGH; Address

and control inputs are switching; Data bus inputs are stable

DD3PS

2222mA

Active nonpower-down standby: 1 bank active; CKE = HIGH; CS

= HIGH;

CK =

CK (MIN); Address and control inputs are switch-

ing; Data bus inputs are stable

DD3N

15 15 15 15 mA 6

Active nonpower-down standby: Clock stopped; 1 bank active;

CKE = HIGH; CS = HIGH; CK = LOW; CK# = HIGH; Address and

control inputs are switching; Data bus inputs are stable

DD3NS

8888mA6

Operating burst read: 1 bank active; BL = 4;

CK =

CK (MIN);

Continuous READ bursts; Iout = 0mA; Address inputs are

switching every 2 clock cycles; 50% data changing each burst

DD4R

115 110 105 100 mA 6

Operating burst write: 1 bank active; BL = 4;

CK =

CK (MIN);

Continuous WRITE bursts; Address inputs are switching; 50%

data changing each burst

DD4W

115 110 105 100 mA 6

Auto refresh: Burst refresh; CKE = HIGH; Ad-

dress and control inputs are switching; Data

bus inputs are stable

RFC = 138ns I

DD5

95 95 95 95 mA 10

RFC =

REFI I

DD5A

3 3 3 3 mA 10, 11

Deep power-down current: Address and control balls are sta-

ble; Data bus inputs are stable

DD8

10 10 10 10 μA 7, 13

512Mb: x16, x32 Mobile LPDDR SDRAM

Electrical Specifications – I

Parameters

PDF: 09005aef83dd2b3e

t67m_512mb_mobile_lpddr.pdf - Rev. I 01/14 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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