JEDEC Standard No. 238
Page 2
3 Organization
The HBM3 DRAM is optimized for high-bandwidth operation to a stack of multiple DRAM devices
across a number of independent interfaces called channels. It is anticipated that each DRAM stack will
support up to 16 channels. Figure 1 shows an example stack containing 4 DRAM dies, each die
supporting 4 channels. Each die contributes additional capacity and additional channels to the stack (up to
a maximum of 16 channels per stack).
Each channel provides access to an independent set of DRAM banks. Requests from one channel may not
access data attached to a different channel. Channels are independently clocked, and need not be
synchronous.
Figure 1 — General Overview of a DRAM Die Stack with Channels
The DRAM vendor may choose to require an optional interface die that sits at the bottom of the stack and
provides signal redistribution and other functions. The vendor may choose to implement many of the
logic functions typically found on DRAM die on this logic die. This standard does not explicitly require
nor prohibit such a solution.
The division of channels among the DRAM dies within a stack is left to the vendor. Figure 1, with the
memory for four channels implemented on each die, is not a required organization. Organizations are
permitted where the memory for a single channel is distributed among multiple dies; however, all
accesses within a single channel must have the same latency for all accesses. Similarly, vendors may
develop products where each memory die can flexibly support 1, 2, 4 or 8 channels – enabling 16-channel
configurations with stacks of 4 to 16 dies while keeping all data for a given channel on one die.
Since each channel is independent, much of this standard will describe a single channel. Where signal
names are involved, families of signals belonging to a given channel will have the suffix a, b, …, p for
channels a through p. If no suffix is present, the signal(s) being described are generic instances of the
various per-channel signals.
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