飞思卡尔MC9S08LG32RM单片机详细英文参考手册

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"MC9S08LG32RM是飞思卡尔（现为NXP半导体）生产的一款基于HCS08内核的8位单片机，该资料为英文版，提供了详尽的技术信息。" 本文档主要介绍了MC9S08LG32和MC9S08LG16单片机的特性，这些器件是飞思卡尔HCS08系列的一部分，具有高效能和低功耗的特点。 ### HCS08微控制器核心 HCS08是一款8位中央处理器单元，具有以下关键特性： 1. **工作频率高达40MHz**：在5.5V至2.7V的电压范围内，CPU可在-40°C到85°C及-40°C到105°C的温度区间内运行，达到较高的处理速度。 2. **HCS08指令集**：包含基础的HCS08指令集，并添加了BGND指令，扩展了编程能力。 3. **丰富的中断/复位资源**：支持多达32个中断/复位源，增强了系统响应性和灵活性。 ### 内置存储器 1. **双阵列闪存**：32KB或18KB的内置闪存，可以在全工作电压和温度范围内进行读、写和擦除操作，确保数据的稳定存储。 2. **随机访问内存(RAM)**：提供1984字节的RAM，满足实时数据处理的需求。 3. **安全电路**：集成的安全电路设计，防止未经授权访问RAM和闪存内容，保障数据安全。 ### 节能模式 - **两种低功耗停止模式**（Stop 2 和 Stop 3）：在待机状态下显著降低功耗。 - **减小功率的等待模式**：在保持部分功能的同时，进一步降低功耗。 - **外围时钟门控寄存器**：可以关闭未使用的模块时钟，减少电流消耗。 - **低功耗片上晶体振荡器(XOSC)**：在低功耗模式下，为实时时钟和液晶控制器提供精确的时钟源。 - **快速唤醒时间**：从Stop 3模式唤醒通常只需要100μs，保证了系统的快速响应。 ### 时钟源与外设 1. **时钟系统**：支持多种时钟源，包括内部振荡器和外部晶体，可以根据应用需求灵活配置。 2. **其他外设**：尽管未在此摘要中详细列出，但HCS08系列通常还包括多种外设，如串行通信接口（UART）、定时器、计数器、模数转换器（ADC）、数字信号处理功能等，为各种应用提供全面的支持。 MC9S08LG32RM是一款针对嵌入式应用设计的高性能、低功耗的8位单片机，适合需要高处理能力、可靠内存保护和节能特性的场合。该单片机的详细规格和用法可从提供的参考手册中获取。

MC9S08LG32 MCU Series, Rev. 5

16 Freescale Semiconductor

Section Number Title Page

Chapter 13

Serial Communications Interface (S08SCIV4)

13.1 Introduction ....................................................................................................................................259

13.1.1 Module Instances ............................................................................................................259

13.1.2 Module Configuration .....................................................................................................259

13.1.3 SCI Clock Gating ............................................................................................................259

13.1.4 Features ...........................................................................................................................261

13.1.5 Modes of Operation ........................................................................................................261

13.1.6 Block Diagram ................................................................................................................262

13.2 Register Definition .........................................................................................................................264

13.2.1 SCI Baud Rate Registers (SCIxBDH, SCIxBDL) ..........................................................264

13.2.2 SCI Control Register 1 (SCIxC1) ...................................................................................265

13.2.3 SCI Control Register 2 (SCIxC2) ...................................................................................266

13.2.4 SCI Status Register 1 (SCIxS1) ......................................................................................267

13.2.5 SCI Status Register 2 (SCIxS2) ......................................................................................269

13.2.6 SCI Control Register 3 (SCIxC3) ...................................................................................270

13.2.7 SCI Data Register (SCIxD) .............................................................................................271

13.3 Functional Description ...................................................................................................................271

13.3.1 Baud Rate Generation .....................................................................................................271

13.3.2 Transmitter Functional Description ................................................................................272

13.3.3 Receiver Functional Description ....................................................................................273

13.3.4 Interrupts and Status Flags ..............................................................................................275

13.3.5 Additional SCI Functions ...............................................................................................276

Chapter 14

Serial Peripheral Interface (S08SPIV4)

14.1 Introduction ....................................................................................................................................278

14.1.1 Module Configuration .....................................................................................................278

14.1.2 SPI Clock Gating ............................................................................................................278

14.1.3 Features ...........................................................................................................................280

14.1.4 Block Diagrams ..............................................................................................................280

14.1.5 SPI Baud Rate Generation ..............................................................................................282

14.2 External Signal Description ...........................................................................................................283

14.2.1 SPSCK — SPI Serial Clock ............................................................................................283

14.2.2 MOSI — Master Data Out, Slave Data In ......................................................................283

14.2.3 MISO — Master Data In, Slave Data Out ......................................................................283

14.2.4 SS

— Slave Select ..........................................................................................................283

14.3 Modes of Operation........................................................................................................................284

14.3.1 SPI in Stop Modes ..........................................................................................................284

14.4 Register Definition .........................................................................................................................284

14.4.1 SPI Control Register 1 (SPIxC1) ....................................................................................284

14.4.2 SPI Control Register 2 (SPIxC2) ....................................................................................285

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Section Number Title Page

14.4.3 SPI Baud Rate Register (SPIxBR) ..................................................................................286

14.4.4 SPI Status Register (SPIxS) ............................................................................................287

14.4.5 SPI Data Register (SPIxD) .............................................................................................288

14.5 Functional Description ...................................................................................................................289

14.5.1 Master Mode ...................................................................................................................289

14.5.2 Slave Mode .....................................................................................................................290

14.5.3 SPI Clock Formats ..........................................................................................................291

14.5.4 Special Features ..............................................................................................................293

14.5.5 SPI Interrupts ..................................................................................................................295

14.5.6 Mode Fault Detection .....................................................................................................295

Chapter 15

Real-Time Counter (S08RTCV1)

15.1 Introduction ....................................................................................................................................297

15.1.1 RTC Clock Gating ..........................................................................................................297

15.1.2 Features ...........................................................................................................................299

15.1.3 Modes of Operation ........................................................................................................299

15.1.4 Block Diagram ................................................................................................................300

15.2 External Signal Description ...........................................................................................................300

15.3 Register Definition .........................................................................................................................300

15.3.1 RTC Status and Control Register (RTCSC) ....................................................................301

15.3.2 RTC Counter Register (RTCCNT) ..................................................................................302

15.3.3 RTC Modulo Register (RTCMOD) ................................................................................302

15.4 Functional Description ...................................................................................................................302

15.4.1 RTC Operation Example .................................................................................................303

15.5 Initialization/Application Information ...........................................................................................304

Chapter 16

Timer/Pulse-Width Modulator (S08TPMV3)

16.1 Introduction ....................................................................................................................................306

16.1.1 TPM External Clock .......................................................................................................306

16.1.2 Module Instances ............................................................................................................306

16.1.3 Module Configuration .....................................................................................................306

16.1.4 TPM Clock Gating ..........................................................................................................307

16.1.5 Features ...........................................................................................................................308

16.1.6 Modes of Operation ........................................................................................................308

16.1.7 Block Diagram ................................................................................................................309

16.2 Signal Description ..........................................................................................................................311

16.2.1 Detailed Signal Descriptions ..........................................................................................311

16.3 Register Definition .........................................................................................................................314

16.3.1 TPM Status and Control Register (TPMxSC) ................................................................314

16.3.2 TPM-Counter Registers (TPMxCNTH:TPMxCNTL) ....................................................315

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Section Number Title Page

16.3.3 TPM Counter Modulo Registers (TPMxMODH:TPMxMODL) ....................................316

16.3.4 TPM Channel n Status and Control Register (TPMxCnSC) ..........................................317

16.3.5 TPM Channel Value Registers (TPMxCnVH:TPMxCnVL) ..........................................318

16.4 Functional Description ...................................................................................................................319

16.4.1 Counter ............................................................................................................................320

16.4.2 Channel Mode Selection .................................................................................................321

16.5 Reset Overview ..............................................................................................................................324

16.5.1 General ............................................................................................................................324

16.5.2 Description of Reset Operation .......................................................................................324

16.6 Interrupts ........................................................................................................................................324

16.6.1 General ............................................................................................................................324

16.6.2 Description of Interrupt Operation .................................................................................325

Chapter 17

Modulo Timer (S08MTIMV1)

17.1 Introduction ....................................................................................................................................327

17.1.1 MTIM Clock Gating .......................................................................................................327

17.1.2 Features ...........................................................................................................................329

17.1.3 Modes of Operation ........................................................................................................329

17.1.4 Block Diagram ................................................................................................................330

17.2 External Signal Description ...........................................................................................................330

17.3 Memory Map and Register Definition ...........................................................................................331

17.3.1 Memory Map (Register Summary) .................................................................................331

17.3.2 Register Descriptions ......................................................................................................331

17.4 Functional Description ...................................................................................................................335

17.4.1 MTIM Operation Example .............................................................................................336

Chapter 18

Development Support

18.1 Introduction ....................................................................................................................................337

18.1.1 Forcing Active Background ............................................................................................337

18.1.2 Module Configuration .....................................................................................................337

18.1.3 Features ...........................................................................................................................338

18.2 Background Debug Controller (BDC) ...........................................................................................338

18.2.1 BKGD Pin Description ...................................................................................................339

18.2.2 Communication Details ..................................................................................................339

18.2.3 BDC Commands .............................................................................................................343

18.2.4 BDC Hardware Breakpoint .............................................................................................345

18.3 Register Definition .........................................................................................................................345

18.3.1 BDC Registers and Control Bits .....................................................................................346

18.3.2 System Background Debug Force Reset Register (SBDFR) ..........................................348

MC9S08LG32 MCU Series, Rev. 5

Freescale Semiconductor 19

Section Number Title Page

Chapter 19

Debug Module (DBG) (64K)

19.1 Introduction ....................................................................................................................................350

19.1.1 Features ...........................................................................................................................350

19.1.2 Modes of Operation ........................................................................................................351

19.1.3 Block Diagram ................................................................................................................351

19.2 Signal Description ..........................................................................................................................352

19.3 Memory Map and Registers ...........................................................................................................352

19.3.1 Module Memory Map .....................................................................................................352

19.3.2 Register Descriptions ......................................................................................................354

19.4 Functional Description ...................................................................................................................365

19.4.1 Comparator .....................................................................................................................365

19.4.2 Breakpoints .....................................................................................................................365

19.4.3 Trigger Selection .............................................................................................................366

19.4.4 Trigger Break Control (TBC) .........................................................................................366

19.4.5 FIFO ................................................................................................................................370

19.4.6 Interrupt Priority .............................................................................................................371

19.5 Resets .............................................................................................................................................371

19.6 Interrupts ........................................................................................................................................371