Verilog 2001有符号运算：新功能与潜在风险

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在Verilog 2001标准中，有符号数值运算被赋予了新的可能性，特别是对于像星键实验室（Starkey Labs）这样的公司，它们在设计和制造复杂的数字助听器时，大量依赖于使用二进制补码表示的有符号数据类型。该文档详细探讨了Verilog 2001中引入的有符号数据类型，包括其二进制补码表示法，如int、shortint、longint等，以及它们如何增强代码的紧凑性和可读性。然而，尽管新特性带来了便利，处理有符号数运算也带来了一些挑战。这些挑战主要包括： 1. 数据扩展（Data Extension）：当进行算术运算时，需要考虑不同数据类型之间的转换可能导致的数据溢出或隐式扩展，这可能会影响计算结果的准确性。 2. 数据截断（Truncation）：在数据转换过程中，如果高位被丢弃，可能会丢失信息，尤其是在处理有符号数的减法运算时，结果可能会出现意外的负值。 3. 舍入（Rounding）：在浮点运算中，有符号数的精确度和舍入规则对结果有着重要影响，设计者需要明确指定或处理可能出现的近似误差。 4. 饱和（Saturation）：在数值超过最大或最小范围时，有符号数运算通常会饱和，防止溢出或下溢，但这也可能影响设计的动态行为。 5. 混合运算（Mixed Sign Operations）：当有符号数与无符号数混合使用时，潜在的边界条件和数据类型的不匹配可能导致未预期的行为，特别是在硬件实现时，可能需要额外的检查或处理策略。 6. 兼容性和一致性：确保设计中的所有工具链，包括仿真器和合成器，能够正确理解和处理这些有符号运算的复杂性，以避免潜在的仿真与实际硬件行为不符的问题。 Verilog 2001标准的有符号运算功能为设计者提供了更多的灵活性，但也需要他们深入理解并妥善处理这些新运算可能带来的潜在风险。遵循"用户谨慎"的原则，设计师需要仔细设计和验证他们的代码，以充分利用这些新特性的同时，避免潜在的错误和效率问题。通过合理使用和适当的设计策略，有符号运算可以显著提升数字信号处理系统的性能和可靠性。

Signed Arithmetic in Verilog 2001 – Opportunities and Hazards

Dr. Greg Tumbush, Starkey Labs, Colorado Springs, CO

Introduction

Starkey Labs is in the business of designing and

manufacturing hearing aids. The new digital hearings aids

we design at the Starkey Labs Colorado IC Design Center

utilize very complex DSP algorithms implemented in both

software and hardware accelerators. The predominant data

type used in these algorithms is signed. The format of the

signed type is two’s complement. The designation of signed

and two’s complement is used interchangeably throughout

this document.

Verilog 2001 provides a very rich set of new signed

data types. However, there are issues when performing

operations such as sign extension, truncation or rounding,

saturation, addition, and multiplication with signed values.

These new data types (in theory) free the designer from

worrying about some of these signed data type issues. More

compact and readable code should result. However, in the

spirit of Verilog, usage of this new functionality is “user

beware”! Arithmetic manipulation between mixes of signed

and unsigned may simulate and synthesize in unintended

ways. Assignments between differently sized types may also

not result in what the designer intended. Does the usage of

signed data types in arithmetic operations result in smaller or

larger circuits?

Verilog 1995 provides only one signed data type,

integer. The rule is that if any operand in an expression is

unsigned the operation is considered to be unsigned. The

rule still applies for Verilog 2001 but now all regs, wires,

and ports can be signed. In addition, a numeric value can be

designated with a ‘s similar to the ‘h hex designation.

Signed functions are also supported as well as the type

casting operators $signed and $unsigned. There are many

new rules about when an operation is unsigned, and some

may surprise you!

In this paper I will provide code examples of how the

new signed data types can be used to create more compact

code if some simple rules are followed. RTL and gate level

simulation results of add and multiply operations using

mixtures of signed and unsigned data types will be provided.

Area results from synthesis using Design Compiler 2003.12

will be presented to compare efficiencies of these

operations. Synthesis warnings that should be investigated

thoroughly will be explained. Suggestions for improvement

in the Verilog 2001 language, such as saturation support,

will also be provided.

Signed Data Types

Table 1 demonstrates the conversion of a decimal value to

a signed 3-bit value in 2’s complement format. A 3-bit signed

value would be declared using Verilog 2001 as signed [2:0]

A;.

Decimal Value Signed Representation

3 3’b011

2 3’b010

1 3’b001

0 3’b000

-1 3’b111

-2 3’b110

-3 3’b101

-4 3’b100

Table 1: Decimal to 3-bit Signed

Type Casting

The casting operators, $unsigned and $signed, only

have effect when casting a smaller bit width to a larger bit.

Casting using $unsigned(signal_name) will zero fill the

input. For example A = $unsigned(B) will zero fill B and

assign it to A. Casting using $signed(signal_name) will

sign extend the input. For example, A = $signed(B). If the

sign bit is X or Z the value will be sign extended using X or

Z, respectively. Assigning to a smaller bit width signal will

simply truncate the necessary MSB’s as usual. Casting to

the same bit width will have no effect other than to remove

synthesis warnings.

Signed Based Values

The only way to declare a signed value in Verilog 1995

was to declare it as an integer which limited the size of the

value to 32-bits only[1]. Verilog 2001 provides the ‘s

construct for declaring and specifying a sized value as

signed. For example, 2 represented as a 3-bit signed hex

value would be specified as 3’sh2. Somewhat confusing is

specifying negative signed values. The value -4 represented

as a 3-bit signed hex value would be specified as -3’sh4. A

decimal number is always signed.

Signed Addition

Adding two values that are n-bits wide will produce a

n+1 bit wide result. The signed values must be sign

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