BCM5461S千兆PHY：一体化电光口解决方案

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"BCM5461S-DS03是博通(BROADCOM)公司的一款千兆以太网收发器，集成了电口（RJ45）与光口，提供10/100/1000BASE-T的传输速率，并兼容多种接口标准，如RGMII、GMII、MII、TBI和RTBI。" BCM5461S是博通公司推出的一款高性能、高度集成的千兆物理层(PHY)芯片，适用于构建高速网络设备。这款器件能够支持1000BASE-T、100BASE-TX/FX以及10BASE-T的以太网通信，允许在标准的Cat5 UTP电缆上实现千兆速度的传输。同时，10BASE-T模式也兼容Cat3、Cat4和Cat5 UTP电缆，提高了其应用的灵活性。该芯片的核心特性之一是其内置的数字自适应均衡器，它能有效地处理信号失真问题，确保在长距离或质量较差的线缆上保持数据传输的稳定性。BCM5461S还包含了模数转换器(ADCs)、锁相环(Phase-Locked Loops)、线路驱动器、编码器、解码器、回声消除器和串扰消除器等关键组件，这些组件共同确保了信号质量和系统的可靠运行。 BCM5461S的设计考虑了与多种以太网媒体访问控制器(MAC)和交换机控制器的兼容性。它支持Rapid Gigabit Media Independent Interface (RGMII)、Gigabit Media Independent Interface (GMII)、Media Independent Interface (MII)、Truncated BIdirectional Interface (TBI)以及Reduced TBI (RTBI)等接口标准。这样的设计使得BCM5461S可以无缝集成到各种基于行业标准的以太网解决方案中。此外，BCM5461S采用了博通先进的数字信号处理技术，确保了设备的合规性和性能，使其能够满足严格的IEEE 802.3ab（1000BASE-T）、802.3u（100BASE-TX/FX）和802.3（10BASE-T）标准。这使得BCM5461S成为构建高带宽、低延迟网络设备的理想选择，如路由器、交换机和服务器接口卡等。 BCM5461S是博通公司为千兆以太网通信提供的一种高效、灵活且兼容性强的解决方案，它的集成化特性减少了外部组件的需求，降低了系统成本，同时也提升了整体性能。无论是对于企业级网络基础设施还是家庭宽带接入，这款芯片都能提供卓越的性能和可靠性。

BCM5461SAdvance Data Sheet

12/09/03

Broadcom Corporation

Page xviDocument5461S-DS03-R

Table 101: Theta-JA vs. Airflow for the PQFP Package..................................................................................................168

Table 102: Theta-JA vs. Airflow for the BGA Package....................................................................................................168

Table 103: Theta-JA vs. Airflow for the FBGA Package.................................................................................................168

4/22/2004D3PMQ

Advance Data Sheet BCM5461S

12/09/03

Broadcom Corporation

Document5461S-DS03-RGigabit Media Independent InterfacePage 3

These modes are hardware pin configured by using the INTF_SEL, EN_10B/SD, and RGMIIEN pins. The following table

lists the available modes that can be selected.

IGABIT

EDIA

NDEPENDENT

NTERFACE

The Gigabit media independent interface (GMII) is the digital data interface between the MAC and the physical layer when

the device is functioning in 1000BASE-T mode. The BCM5461S GMII contains all the signals required to transmit and

receive data at Gigabit speeds for both full-duplex and half-duplex operation. The transmit signals include TX_EN, GTXCLK,

TXD[7:0], and TX_ER. The receive signals include RX_DV, RXC, RXD[7:0], and RX_ER. The medium status signals include

CRS and COL.

Table 1:

Hardware Mode Selection

Hardware StrappingMAC InterfaceMedia Interface

INTF_SEL[1:0]EN_10B/SDRGMIIENGMIITBI

2.5V

RGMII

2.5V

RTBI

SGMIIGBICCopperSerDes

10XXXX

11XXXXX

Note:

The SerDes media interface is automatically put into power-down mode, and bit 1 is set to 1 in the 1000BASE-X MII

Control register 00h. (This register is enabled by writing to the Mode Control register 1Ch, shadow value 11111,

bit0=1, and then by accessing register 00h.) The SerDes media interface is not put into power-down mode when

AUTODET pin is strapped active high, upon hardware reset.

The Copper media interface is automatically put into power-down mode (1000BASE-T/100BASE-TX/10BASE-T MII

Control register 00h, bit11=1). (This register is enabled by writing to the Mode Control register 1Ch, shadow value

11111, bit 0 = 0, and then by accessing register 00h.) The Copper media interface is not put into power-down mode

when AUTODET pin is strapped active high, upon hardware reset.

When AUTODET pin is strapped active high, the TBI and RTBI MAC interfaces will not be selected from the hardware

strappings upon hardware reset. They can be selected through software.

4/22/2004D3PMQ

BCM5461SAdvance Data Sheet

12/09/03

Broadcom Corporation

Page 4Reduced Gigabit Media Independent InterfaceDocument5461S-DS03-R

EDIA

NDEPENDENT

NTERFACE

The media independent interface (MII) is the digital data interface between the MAC and the physical layer when the device

is functioning in 10BASE-T and 100BASE-TX modes. The BCM5461S MII contains all the signals required to transmit and

receive data at 100 Mbps and 10 Mbps for both full-duplex and half-duplex operation. The transmit signals include TX_EN,

TXC, TXD[3:0], and TX_ER. The receive signals include RX_DV, RXC, RXD[3:0], and RX_ER. The media status signals

include CRS and COL.

EDUCED

IGABIT

EDIA

NDEPENDENT

NTERFACE

The reduced gigabit media independent interface (RGMII) is a subset of GMII, which allows the MAC with a reduced pin

count to connect to the PHY. If this interface is active, the number of data signal pins required to and from the MAC is reduced

to half by clocking data on both the rising and falling edge of the transmit clock. This makes the RGMII digital data bit

transmission rate effectively twice that of the GMII, while the clock speed remains the same. The RGMII and GMII interfaces

use the same hardware and internal circuitry, though only TXD[3:0] and RXD[3:0] signals are used in RGMII mode. For more

information about this mode, see ”RGMII Interface” on page 38.

10-B

NTERFACE

The BCM5461S can interface directly with Ethernet MACs that support 10-Bit Interface (TBI) used by standard fiber-optic

SerDes chips. In the TBI mode, the GMII signals are replaced with 10-bit encoded transmit and receive data words. The

TX_ER, TX_EN, RX_DV, and RX_ER pins compose the additional signal lines required in TBI mode.

EDUCED

10-B

NTERFACE

The BCM5461S can communicate directly to Ethernet MACs that support the reduced 10-bit interface (RTBI). These MACs

transmit and receive data on both the rising and falling edge of the data clocks. The 10 signal lines required in TBI mode are

reduced to 5 in each direction in RTBI mode. RTBI uses TXD[3:0], RXD[3:0], RX_ER, RX_DV, TX_ER, and TX_EN data

signals, and GTXCLK and RXC clock signals.

ERIAL

GMII I

NTERFACE

The BCM5461S can communicate with Ethernet MACs that support the SGMII interface. The serial GMII (SGMII) interface

transmits serial data differentially at 1.25 gigabaud via the SGOUT± pin and receives serial data differentially via the

SGIN±pin, which includes an on-chip 100Ω differential termination resistor. In SGMII mode, serial output data is clocked on

both edges of a differential 625-MHz clock via the SCLK± pin. Because the BCM5461S provides clock recovery on the SGMII

input data, the input clock is not required. The SGMII interface pins are shared with the SerDes interface pins described in

”SerDes Interface (Complies with IEEE 802.3, Clauses 36 and 37)” on page 5.

This serial interface can also connect to any SerDes-compatible media device (such as a fiber module) to allow transmission

to and from a link partner. For additional information regarding the SGMII/SerDes interface, refer to the BCM5461S Design

Guide.

4/22/2004D3PMQ

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