20-6
A 25mA CMOS LDO with í85dB PSRR at 2.5MHz
Jianping Guo
1, 2
and Ka Nang Leung
1
1
Department of Electronic Engineering, The Chinese University of Hong Kong, Hong Kong, China
2
School of Physics and Engineering, Sun Yat-sen University, Guangzhou, China
Email: guojp3@mail.sysu.edu.cn; knleung@ee.cuhk.edu.hk
Abstract—A CMOS low-dropout regulator (LDO) with high
power-supply rejection ratio (PSRR) achieved by the proposed
supply ripple feed-forward path is presented in this paper. The
LDO is simple with two additional low-pass filters included. No
extra power is consumed when comparing to the traditional
design. The proposed LDO is implemented in 0.18-
μ
m CMOS
technology. It occupies active area of 0.042 mm
2
. With the
proposed embedded supply ripple feed-forward path, in the
maximum loading of 25 mA, it achieves PSRR of í85 dB at 2.5
MHz and PSRR better than í55 dB when frequency is below 5
MHz with a 4.7-
μ
F output capacitor. The measured quiescent
current is 15
μ
A only. The overshoot and undershoot voltages are
less than 40 mV when loading changes between 1 mA and 25 mA
within 40 ns. The LDO achieves line and load regulations of 3
mV/V and 50
μ
V/mA, respectively.
Keywords—low-dropout regulator, power-supply rejection ratio,
supply ripple cancellation, embedded feed-forward path, transient
response.
I. INTRODUCTION
Ripple-free power supply is essential for all noise-sensitive
analogue and RF circuits. For a system with supply noise,
power-supply ripple rejection (PSRR) is definitely a dominant
performance to the dynamic performance of ADC [1], and it
also affects the jitter performance of clock generation circuits
[2], [3]. Low-dropout regulator (LDO) with high PSRR is a
suitable choice as a post regulator for switched-mode DC-DC
converter to provide clean voltage source. However, with the
increase of switching frequency to several MHz or even up to
several tens of MHz to reduce PCB area and component cost
[4], [5], LDO with high PSRR over wide frequency spectrum
is required. Modern wireless communication standards feature
wider signal bandwidth. For example, signal bandwidth in
WiMAX systems ranges from 1.25 MHz to 28 MHz [6]. To
meet the stricter requirements of the transmission mask, LDO
should have low noise by eliminating ripples at the supply rail
over a wide range of frequency spectrum [7].
Traditional methods to design high-PSRR LDO include
designing a high-precision error amplifier (EA) with very
wide bandwidth to enhance the negative feedback at high
frequency. Another method is to stack more power transistors
to enhance the isolation between supply rail and LDO output
[8]−[10]. However, quiescent current (I
Q
) or dropout voltage
(V
DO
) is increased to make efficiency degraded. The stacked
power transistors occupy much more chip area and cost.
The main idea behind some existing methods to achieve
high PSRR is to provide a signal path to duplicate the supply
ripples to the gate of the power transistor to have ripple
cancellation [11]í[14]. A voltage subtractor achieved by a
diode-connected transistor between the supply and the gate of
power transistor was adopted to improve PSRR in the low-
frequency range [11]. Current-mode LDO was proposed to
enhance the PSRR at high frequency with the cost of more
than 180-pF on-chip capacitance, which leads to 1.2-mm
2
chip
area in 1.5-ȝm bipolar technology [12]. A CMOS LDO by
using a feed-forward path can achieve high PSRR better than
í56 dB up to 10 MHz [13]. Although the high-bandwidth
error amplifier is not needed in [13], the feed-forward
amplifier and the summing amplifier consume more power to
achieve high-bandwidth operation for regenerating the high-
frequency ripples to the gate of power transistor.
Based on above considerations, an embedded feed-forward
path (EFFP) is proposed to extract ripples from the supply rail
and regenerate the ripples to the gate of power transistor to
improve PSRR. The proposed structure simply reuses the
buffer stage in the conventional LDO, and thus no additional
static power is consumed. Only two low-pass filters (LPFs) are
added. Results will show that the LDO’s PSRR can be
improved effectively up to several MHz. Detailed descriptions
and analysis of the proposed EFFP technique will be presented
in Section II. The circuit implementation and design
considerations will be provided in Section III. Then, the
experimental results will be given in Section IV. Finally,
Section V gives the conclusions of this paper.
II. P
ROPOSED EMBEDDED FEED-FORWARD PATH
The block diagram of proposed LDO is shown in Fig. 1.
Only two transistors, M
2
and M
1
, in the same single current
branch, are used to conduct the functions of the feed-forward
amplifier and summing amplifier as the design reported in [13].
Considering M
2
as a common-gate amplifier, the input supply
ripple is fed forward to the gate of power transistor M
P
with a
DC voltage gain of g
m2
/g
m1
since its output is terminated by the
source of M
1
, where g
m2
and g
m1
are the transconductance of
M
2
and M
1
, respectively. A low-pass filter (LPF) is introduced
to shunt the gate of M
2
to the AC ground and thus this makes it
operate as a common-gate amplifier above the corner
frequency of the LPF. The ripple voltage appearing at the gate
of M
P
can be set to close to supply ripple by setting the proper
size ratio of M
2
to M
1
. Thus, the source-gate voltage of M
P
is
free of ripples, and the LDO’s PSRR can be improved.
This work was partly supported
b
y a grant from the Research Grant
Council of Hong Kong SAR Government under CUHK414210 and a grant
from National Natural Science Foundation of China under 61204035.
381
978-1-4799-0280-4/13/$31.00
c
2013 IEEE
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