VHDL编程入门：实例详解

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"《VHDL编程：实例详解》(Douglas L. Perry著，第四版)，这是一本关于VHDL编程的老牌经典书籍，虽然出版时间较早，但内容详实，提供了丰富的示例，是学习VHDL语言的理想参考资料。" VHDL（Very High-Speed Integrated Circuit Hardware Description Language）是一种硬件描述语言，被广泛用于数字系统的设计和仿真，包括集成电路、FPGA（Field-Programmable Gate Array）和ASIC（Application-Specific Integrated Circuit）等。本书由Douglas L. Perry编写的第四版，尽管出版年份较早，但其内容依然具有很高的参考价值。该书的核心特点是通过实例教学，使读者能够更好地理解和掌握VHDL的语法和应用。实例是学习任何编程语言的关键，尤其对于VHDL这样的专业语言，实践案例可以帮助读者将理论知识转化为实际操作能力。书中涵盖的实例可能包括基本的逻辑门、触发器、计数器、移位寄存器、处理器等数字电路设计，以及更复杂的系统级设计。 VHDL的特点包括： 1. **数据类型丰富**：VHDL支持多种数据类型，如std_logic、std_logic_vector等，可以描述各种数字信号状态。 2. **结构化编程**：支持过程（procedure）、函数（function）、包（package）等结构，便于代码组织和复用。 3. **并行处理**：VHDL的并发语句使得设计可以并行执行，符合硬件系统的运行方式。 4. **设计层次化**：可以从最底层的门级到顶层的系统级进行设计，方便模块化和重用。学习VHDL，读者需要了解以下关键概念： - **实体（Entity）**：定义硬件接口，描述输入/输出信号。 - **结构体（Architecture）**：定义实体的行为，实现逻辑功能。 - **库（Library）**：包含预定义的组件和数据类型。 - **进程（Process）**：描述时序逻辑，模拟硬件的行为。 - **类型和信号（Type and Signal）**：类型定义数据格式，信号用于在设计内部传递信息。 - **函数和过程**：函数用于计算，过程用于控制流程。此外，书中可能还涉及到了VHDL的仿真和综合过程，这是将VHDL设计转化为可实现硬件的重要步骤。仿真允许设计师在硬件制造前验证设计的正确性，而综合工具则会将VHDL代码转换为特定目标器件的门级网表。《VHDL编程：实例详解》是一本对初学者和有经验的设计师都非常有价值的资源，它通过大量实例帮助读者深入理解VHDL的各个方面，从而提升设计和实现数字系统的能力。尽管出版年份较早，但VHDL的基础语法和设计理念并未有过大的变化，因此这本书的内容仍然具有很高的实用性和指导意义。

PREFACE

This is the fourth version of the book and this version now not only provides

VHDL language coverage but design methodology information as well. This

version will guide the reader through the process of creating a VHDL

design, simulating the design, synthesizing the design, placing and routing

the design, using VITAL simulation to verify the final result, and a new

technique called At-Speed debugging that provides extremely fast design

verification. The design example in this version has been updated to reflect

the new focus on the design methodology.

This book was written to help hardware design engineers learn how to

write good VHDL design descriptions. The goal is to provide enough VHDL

and design methodology information to enable a designer to quickly write

good VHDL designs and be able to verify the results. It will also attempt

to bring the designer with little or no knowledge of VHDL, to the level of

writing complex VHDL descriptions. It is not intended to show every pos-

sible construct of VHDL in every possible use, but rather to show the de-

signer how to write concise, efficient, and correct VHDL descriptions of

hardware designs.

This book is organized into three logical sections. The first section of the

book will introduce the VHDL language, the second section walks through

a VHDL based design process including simulation, synthesis, place and

route, and VITAL simulation; and the third section walks through a design

example of a small CPU design from VHDL capture to final gate-level

implementation, and At-Speed debugging. At the back of the book are

included a number of appendices that contain useful information about the

language and examples used throughout the book.

In the first section VHDL features are introduced one or more at a time.

As each feature is introduced, one or more real examples are given to show

how the feature would be used. The first section consists of Chapters 1

through 8, and each chapter introduces a basic description capability of

VHDL. Chapter 1 discusses how VHDL design relates to schematic based

design, and introduces the basic terms of the language. Chapter 2 describes

some of the basic concepts of VHDL, including the different delay mecha-

nisms available, how to use instance specific data, and defines VHDL dri-

vers. Chapter 2 discusses concurrent statements while Chapter 3 introduces

the reader to VHDL sequential statements. Chapter 4 talks about the wide

Preface

xvi

range of types available for use in VHDL. Examples are given for each of

the types showing how they would be used in a real example. In Chapter

5 the concepts of subprograms and packages are introduced. The different

uses for functions are given, as well as the features available in VHDL

packages.

Chapter 6 introduces the five kinds of VHDL attributes. Each attribute

kind has examples describing how to use the specific attribute to the

designer’s best advantage. Examples are given which describe the pur-

pose of each of the attributes.

Chapters 7 and 8 will introduce some of the more advanced VHDL

features to the reader. Chapter 7 discusses how VHDL configurations

can be used to construct and manage complex VHDL designs. Each of

the different configuration styles are discussed along with examples

showing usage. Chapter 8 introduces more of the VHDL advanced top-

ics with discussions of overloading, user defined attributes, generate

statements, and TextIO.

The second section of the book consists of Chapters 9 through 11. Chap-

ters 9 and 10 discuss the synthesis process and how to write synthesiz-

able designs. These two chapters describe the basics of the synthesis

process including how to write synthesizeable VHDL, what is a technol-

ogy library, what does the synthesis process look like, what are con-

straints and attributes, and what does the the optimization process look

like. Chapter 11 discusses the complete high level design flow from VHDL

capture through VITAL simulation.

The third section of the book walks through a description of a small

CPU design from the VHDL capture through simulation, synthesis, place

and route, and VITAL simulation. Chapter 12 describes the top level of

the CPU design from a functional point of view. In Chapter 13 the RTL

description of the CPU is presented and discussed from a synthesis point

of view. Chapter 14 begins with a discussion of VHDL testbenches and

how they are used to verify functionality. Chapter 14 finishes the discus-

sion by describing the simulation of the CPU design. In Chapter 15 the

verified design is synthesized to a target technology. Chapter 16 takes

the synthesized design and places and routes the design to a target

device. Chapter 17 begins with a discussion of VITAL and ends with the

VITAL simulation of the placed and routed CPU design. Chapter 18 is a

new chapter that discusses the new technique of At-Speed debugging.

This chapter provides the reader with an in-depth look at how a hardware

implementation of the CPU design can help speed verification.

Finally there are three appendices at the end of the book to provide ref-

erence information. Appendix A is a listing of the IEEE 1164 STD_LOGIC

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