Figure 2. Edge Detection in Color Images using Sobel Operator
The streaming data processing cannot be used because the edge
detection using Sobel operator algorithm is window based operation.
Therefore, input data from camera is stored in on-chip memory (BRAM and
Registers) before processing it on FPGA. The Sobel edge detection logic
can begin processing as soon as two rows arrived in Buffer Memory. The
Smart Buffer based Buffer Memory architecture [18] is used in the
proposed Sobel operator based color edge detection implementation for
data buffering. This approach (Fig. 3) works if one image pixel is
coming from camera interface module in one clock cycle. The pixels are
coming row by row. When buffers are filled, this architecture provides
the access to the entire pixel neighborhood every clock cycle. The
architecture places the highest demand on internal memory bandwidth.
Because modern FPGA devices contain large amount of embedded memory,
this approach does not cause problems [19]. The length of the shift
registers depends on the width of input image. For
PAL (720x576) size images the length of FIFOs is 717 (i.e. 720 - 3).
For CIF (352x288) size images, it is 349 (i.e. 352 – 3).