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首页S3C6410微处理器用户手册v1.2:修订版1.20,2009年发布
S3C6410微处理器用户手册v1.2:修订版1.20,2009年发布
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S3C6410X是一款由三星电子有限公司设计的RISC微处理器,其用户手册版本为v1.2,发布日期为2009年2月13日。此文档提供了对S3C6410X芯片的详细技术规格、功能描述以及使用指南,旨在帮助开发者理解和操作这款处理器。
手册的重要注意事项强调了信息的准确性,虽然在出版时已经进行了仔细校验,但三星并不对可能存在的错误或遗漏负责,并且保留随时根据需要改进产品功能或设计的权利,而无需提前通知用户更新手册。这意味着用户在使用过程中可能会遇到新的功能或接口变更,因此建议定期查阅最新的官方资料。
手册还指出,购买S3C6410X半导体器件的用户并不能通过这份文档获得任何专利使用权的许可。三星明确声明,对其产品的适用性不作任何保证,也不承担因特定用途而产生的责任。此外,三星特别排除了所有责任,包括但不限于因应用或使用任何产品或电路而产生的任何责任,这表明用户需自行评估产品在具体应用中的性能和安全性。
在阅读和使用S3C6410X英文手册时,读者应关注以下几个关键部分:
1. **架构和特性**:了解处理器的基本架构、核心功能,如CPU指令集、内存管理、外设接口等。
2. **引脚定义和功能**:每个引脚的电气特性、功能分配以及如何连接外部设备。
3. **寄存器和控制**:学习如何通过寄存器来配置和管理处理器状态,如中断系统、定时器和计数器等。
4. **电源管理和时钟管理**:了解处理器的电源需求、时钟设置以及节能模式。
5. **调试和编程工具**:熟悉与该处理器配合使用的开发工具和接口,以便进行软件开发和调试。
6. **安全性和加密措施**:如果手册涉及,了解关于安全特性和数据保护机制的相关信息。
7. **错误处理和故障诊断**:学习如何识别和处理可能出现的错误,以及如何利用内置的诊断功能进行问题排查。
8. **更新和兼容性**:确认手册是否包含针对后续版本的兼容性说明,以及可能的软件升级路径。
S3C6410X英文手册是开发人员和系统设计师必不可少的参考资料,它详细阐述了如何充分利用这款高性能的RISC微处理器,确保系统设计和应用的顺利进行。在使用时,务必遵循手册中的指导,同时注意可能的更新和变化。
![](https://csdnimg.cn/release/download_crawler_static/4013901/bg10.jpg)
xvi S3C6410X_USER’S MANUAL_REV 1.20
Table of Contents (Continued)
Chapter 14 Display Controller
14.4.5 Palette usage .................................................................................................................................14-16
14.4.5.1 Palette Configuration and Format Control..............................................................................14-16
14.4.6 Window Blending ...........................................................................................................................14-18
14.4.6.1 Overview.................................................................................................................................14-18
14.4.6.2 Blending Diagram/Details ...........................................................................................................14-20
14.4.7 COLOR-KEY Function...................................................................................................................14-22
14.4.8 VTIME CONTROLLER OPERATION ............................................................................................14-25
14.4.8.1 RGB Interface.........................................................................................................................14-25
14.4.8.2 I80 Interface Controller..........................................................................................................14-26
14.4.9 LDI Command Control ...................................................................................................................14-27
14.4.9.1 Auto Command.......................................................................................................................14-27
14.4.9.2 Normal Command ..................................................................................................................14-27
14.4.10 I80 CPU Interface Trigger............................................................................................................14-29
14.4.11 Interrupt........................................................................................................................................14-29
14.4.12 Virtual Display ..............................................................................................................................14-29
14.4.13 RGB Interface IO .........................................................................................................................14-31
14.4.14 LCD I80 INTERFACE IO..............................................................................................................14-32
14.4.14 ITU-R BT.601 INTERFACE IO.....................................................................................................14-33
14.4.15 LCD DaTA PiN MAP....................................................................................................................14-34
14.4.16 LCD NORMAL/BY-PASS MODE SELECTION ...........................................................................14-36
14.5 Programmer’s Model.............................................................................................................................14-37
14.5.1 Overview
........................................................................................................................................14-37
14.5.2 SFR Memory Map..........................................................................................................................14-37
14.6 Individual Register Descriptions............................................................................................................14-40
14.6.1 Video Main Control 0 Register.......................................................................................................14-40
14.6.2 Video Main Control 1 Register.......................................................................................................14-42
14.6.3 Video Main Control 2 Register.......................................................................................................14-43
14.6.4 VIDEO Time Control 0 Register.....................................................................................................14-43
14.6.5 Video Time Control 1 Register.......................................................................................................14-44
14.6.6 VIDEO Time Control 2 Register.....................................................................................................14-44
14.6.7 Window 0 Control Register ............................................................................................................14-44
14.6.8 Window 1 Control Register ...........................................................................................................14-46
14.6.9 Window 2 Control Register ............................................................................................................14-48
14.6.10 Window 3 Control Register ..........................................................................................................14-50
14.6.11 Window 4 Control Register ..........................................................................................................14-51
14.6.12 Window 0 Position Control A Register.........................................................................................14-52
14.6.13 Window 0 Position Control B Register.........................................................................................14-52
14.6.14 Window 0 Position Control C Register.........................................................................................14-52
14.6.15 Window 1 Position Control A Register.........................................................................................14-53
14.6.16 Window 1 Position Control B Register.........................................................................................14-53
14.6.17 Window 1 Position Control C Register........................................................................................14-54
14.6.18 Window 1 Position Control D Register
.........................................................................................14-54
14.6.19 Window 2 Position Control A Register.........................................................................................14-54
![](https://csdnimg.cn/release/download_crawler_static/4013901/bg11.jpg)
S3C6410X_USER’S MANUAL_REV 1.20 xvii
Table of Contents (Continued)
Chapter 14 Display Controller
14.6.20 Window 2 Position Control B Register ........................................................................................14-55
14.6.21 Window 2 Position Control C Register ........................................................................................14-55
14.6.22 Window 2 Position Control D Register ........................................................................................14-55
14.6.23 Window 3 Position Control A Register ........................................................................................14-56
14.6.24 Window 3 Position Control B Register ........................................................................................14-56
14.6.25 Window 3 Position Control C Register ........................................................................................14-57
14.6.26 Window 4 Position Control a Register.........................................................................................14-57
14.6.27 Window 4 Position Control B Register ........................................................................................14-58
14.6.28 Window 4 Position Control C Register ........................................................................................14-58
14.6.29 FRAME Buffer Address 0 Register..............................................................................................14-59
14.6.30 FRAME Buffer Address 1 Register..............................................................................................14-59
14.6.31 FRAME Buffer Address 2 Register..............................................................................................14-60
14.6.32 VIDEO interrupt Control 0 Register .............................................................................................14-60
14.6.33 VIDEO interrupt Control 1 Register .............................................................................................14-61
14.6.34 Win1 Color Key 0 Register ..........................................................................................................14-62
14.6.35 WIN 1 Color key 1 Register.........................................................................................................14-62
14.6.36 Win2 Color Key 0 Register ..........................................................................................................14-63
14.6.37 WIN2 Color key 1 Register..........................................................................................................14-63
14.6.38 Win3 Color Key 0 Register ..........................................................................................................14-64
14.6.39 WIN3 Color k
ey 1 Register..........................................................................................................14-64
14.6.40 Win4 Color Key 0 Register ..........................................................................................................14-65
14.6.41 WIN4 Color key 1 Register..........................................................................................................14-66
14.6.42 Dithering Control 1 Register ........................................................................................................14-67
14.6.43 WIN0 Color MAP .........................................................................................................................14-67
14.6.44 WIN1 Color MAP .........................................................................................................................14-68
14.6.44 WIN1 Color MAP .........................................................................................................................14-68
14.6.45 WIN2 Color MAP .........................................................................................................................14-68
14.6.46 WIN3 Color MAP .........................................................................................................................14-68
14.6.47 WIN4 Color MAP .........................................................................................................................14-69
14.6.48 Window Palette control Register .................................................................................................14-69
14.6.49 I80 / RGB Trigger Control Register .............................................................................................14-70
14.6.50 ITU 601 Interface control 0..........................................................................................................14-70
14.6.51 LCD I80 Interface Control 0.........................................................................................................14-71
14.6.52 LCD I80 Interface Control 1.........................................................................................................14-72
14.6.53 LCD I80 Interface Command Control 0.......................................................................................14-72
14.6.54 LCD I80 Interface Command Control 1.......................................................................................14-74
14.6.55 I80 System Interface Manual Command Control 0 .....................................................................14-74
14.6.56 I80 System Interface Manual Command Control 1 .....................................................................14-75
14.6.57 I80 System Interface Manual Command Control 2 .....................................................................14-75
14.6.58 LCD I80 Interfac
e Command.......................................................................................................14-76
14.6.59 Window 2’s Palette Data .............................................................................................................14-76
14.6.60 Window 3’s Palette Data .............................................................................................................14-77
14.6.61 Window 4’s Palette Data .............................................................................................................14-77
14.6.62 WIN0 Palette Ram Access Address (not SFR) ...........................................................................14-77
14.6.63 WIN1 Palette Ram Access Address (not SFR) ...........................................................................14-78
![](https://csdnimg.cn/release/download_crawler_static/4013901/bg12.jpg)
xviii S3C6410X_USER’S MANUAL_REV 1.20
Table of Contents (Continued)
Chapter 15 Post Processor
15.1 Overview................................................................................................................................................15-1
15.2 Features ................................................................................................................................................15-2
15.3 A Source and Destination Image Data Format .....................................................................................15-3
15.3.1 DMA Mode Operation ....................................................................................................................15-4
15.3.2 FIFO Mode Operation....................................................................................................................15-7
15.4 Image Size and Scale Ratio..................................................................................................................15-7
15.5 DMA operation of Source and Destination Image.................................................................................15-9
15.5.1 Start address..................................................................................................................................15-10
15.5.2 End address...................................................................................................................................15-10
15.6 Frame Management of POST Processor..............................................................................................15-12
15.6.1 Per Frame Management Mode......................................................................................................15-12
15.6.2 Free Run Mode ..............................................................................................................................15-12
15.7 Register File Lists..................................................................................................................................15-13
15.7.1 MODE Control Register .................................................................................................................15-15
15.7.3 Pre-Scale Image Size Register......................................................................................................15-17
15.7.4 Source Image Size Register ..........................................................................................................15-18
15.7.5 Horizontal Main Scale Ratio Register ............................................................................................15-18
15.7.6 Vertical Main Scale Ratio Register ................................................................................................15-18
15.7.7 Destination Image Size Register ...................................................................................................15-19
15.7.8 Pre-Scale Shift Factor Register .....................................................................................................15-19
15.7.9 DMA Start Address Register..........................................................................................................20
15.7.10 DMA End Addres
s Register.........................................................................................................15-21
15.7.11 Current Frame(Buffer0) and Next Frame(Buffer1) Offset Register .............................................15-22
15.7.12 Next Frame DMA Start Address Register....................................................................................15-23
15.7.13 Next Frame DMA End Address Register.....................................................................................15-24
15.7.14 DMA Start address Register for Output Cb and Cr .....................................................................15-24
15.7.15 DMA End Address Register for Output Cb and Cr ......................................................................15-25
15.7.16 Current Frame(Buffer0) and Next Frame(Buffer1) Offset Register for Output Cb and Cr ..........15-25
15.7.17 15.26 Next Frame DMA Start Address Register for Output Cb and Cr.......................................15-25
15.7.18 Next Frame DMA End Address Register for Output Cb and Cr ..................................................15-26
15.7.19 POSTENVID Register to Enable Video Processing ....................................................................15-26
15.7.20 MODE Control Register 2 ............................................................................................................15-27
![](https://csdnimg.cn/release/download_crawler_static/4013901/bg13.jpg)
S3C6410X_USER’S MANUAL_REV 1.20 xix
Table of Contents (Continued)
Chapter 16 TV Scaler
16.1 Overview ...............................................................................................................................................16-1
16.2 Features................................................................................................................................................16-2
16.3 A Source and Destination Image Data Format.....................................................................................16-3
16.3.1 DMA Mode Operation....................................................................................................................16-4
16.3.2 FIFO Mode Operation....................................................................................................................16-7
16.4 Image Size and Scale Ratio..................................................................................................................16-7
16.5 DMA operation of Source and Destination Image ................................................................................16-9
16.5.1 Start address .................................................................................................................................16-10
16.5.2 End address...................................................................................................................................16-10
16.6 Frame Management of TV Scaler.........................................................................................................16-12
16.6.1 Per Frame Management Mode......................................................................................................16-12
16.6.2 Free Run Mode..............................................................................................................................16-12
16.7 Register File Lists .................................................................................................................................16-13
16.7.1 MODE Control Register.................................................................................................................16-15
16.7.3 Pre-Scale Image Size Register .....................................................................................................16-17
16.7.4 Source Image Size Register..........................................................................................................16-18
16.7.5 Horizontal Main Scale Ratio Register............................................................................................ 16-18
16.7.6 Vertical Main Scale Ratio Register................................................................................................16-18
16.7.7 Destination Image Size Register ...................................................................................................16-19
16.7.8 Pre-Scale Shift Factor Register.....................................................................................................16-19
16.7.9 DMA Start Address Register .........................................................................................................16-20
16.7.10 DMA End Addres
s Register.........................................................................................................16-20
16.7.11 Current Frame (Buffer0) and Next Frame (Buffer1) Offset Register...........................................16-21
16.7.12 Next Frame DMA Start Address Register ...................................................................................16-21
16.7.13 Next Frame DMA End Address Register.....................................................................................16-22
16.7.14 DMA Start Address Register for Output Cb and Cr.....................................................................16-22
16.7.15 DMA End Address Register for Output Cb and Cr......................................................................16-23
16.7.16 Current Frame (Buffer0) and Next Frame (Buffer1) Offset Register for Output Cb and Cr ........16-23
16.7.17 Next Frame DMA Start Address Register for Output Cb and Cr.................................................16-23
16.7.18 Next Frame DMA End Address Register for Output Cb and Cr..................................................16-24
16.7.19 POSTENVID Register for Enable Video Processing...................................................................16-24
16.7.20 MODE Control Register 2............................................................................................................16-25
![](https://csdnimg.cn/release/download_crawler_static/4013901/bg14.jpg)
xx S3C6410X_USER’S MANUAL_REV 1.20
Table of Contents (Continued)
Chapter 17 TV Encoder
17.1 Overview................................................................................................................................................17-1
17.2 Feature ..................................................................................................................................................17-1
17.3 Block Diagram .......................................................................................................................................17-2
17.4 Functional Descriptions.........................................................................................................................17-3
17.4.1 Composition Of Analog Composite Signal.....................................................................................17-4
17.4.2 Common Ntsc System ...................................................................................................................17-5
17.4.3 Common Pal System .....................................................................................................................17-6
17.4.4 Composition Of Screen..................................................................................................................17-7
17.4.5 Requested Horizontal Timing ........................................................................................................17-8
17.4.6 Requested Vertical Timing.............................................................................................................17-9
17.5 Dac Board Configure Guide ..................................................................................................................17-10
17.6 Tv Encoder Register Summary .............................................................................................................17-11
17.7 Individual Register Descriptions............................................................................................................17-12
17.7.1 TVENCREG1 .................................................................................................................................17-12
17.7.2 TVENCREG2 .................................................................................................................................17-13
17.7.3 TVENCREG3 .................................................................................................................................17-13
17.7.4 TVENCREG4 .................................................................................................................................17-13
17.7.5 TVENCREG5 .................................................................................................................................17-14
17.7.6 TVENCREG6 .................................................................................................................................17-14
17.7.7 TVENCREG7 .................................................................................................................................17-14
17.7.8 TVENCREG8 .................................................................................................................................17-15
17.7.9 TVENCREG9 .................................................................................................................................17-15
17.7.10 TVENCREG10
.............................................................................................................................17-16
17.7.11 TVENCREG11 .............................................................................................................................17-16
17.7.12 TVENCREG12 .............................................................................................................................17-16
17.7.13 TVENCREG14 .............................................................................................................................17-17
17.7.14 TVENCREG15 .............................................................................................................................17-17
17.7.15 TVENCREG18 .............................................................................................................................17-19
17.7.16 TVENCREG19 .............................................................................................................................17-19
17.7.17 TVENCREG20 .............................................................................................................................17-20
17.7.18 TVENCREG21 .............................................................................................................................17-21
17.7.19 TVENCREG23 .............................................................................................................................17-21
17.7.20 TVENCREG25 .............................................................................................................................17-22
17.7.21 TVENCREG26 .............................................................................................................................17-23
17.7.22 TVENCREG27 .............................................................................................................................17-23
17.7.23 TVENCREG28 .............................................................................................................................17-24
17.7.24 TVENCREG29 .............................................................................................................................17-24
17.7.25 TVENCREG30 .............................................................................................................................17-24
17.7.26 TVENCREG31 .............................................................................................................................17-25
17.7.27 TVENCREG32 .............................................................................................................................17-25
17.7.28 TVENCREG33 .............................................................................................................................17-25
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