"HDMI协议 Version 2.1详解与规范解析"

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HDMI协议版本2.1是由HDMI论坛发布的高清晰度多媒体接口规范的最新版本。该规范包含了478页的内容，涵盖了诸多技术细节和标准。 HDMI协议版本2.1的发布代表了高清晰度多媒体接口技术的最新进展。该规范的发布日期为机密信息，这意味着只有授权人员才能获取这一信息。HDMI协议版本2.1的发布标志着HDMI论坛持续致力于推动高清晰度多媒体接口技术的发展，并且为消费者提供更好的音视频体验。 HDMI协议版本2.1的发布对于消费者来说意味着什么呢？首先，这意味着更高的分辨率和更高的图像质量。HDMI协议版本2.1支持8K分辨率和更高的帧率，这意味着消费者可以享受更清晰、更流畅的画面。此外，HDMI协议版本2.1还支持动态HDR，这意味着消费者可以在观看高清视频时获得更好的色彩表现和对比度。除了更高的分辨率和更好的图像质量，HDMI协议版本2.1还带来了更大的带宽。新的规范支持48Gbps的带宽，这意味着可以传输更多的数据，包括更高的分辨率、更高的帧率和更多的音频通道。这为消费者提供了更大的灵活性，可以满足不同场景下的需求。除了以上提到的技术特性，HDMI协议版本2.1还支持自适应帧同步、变量刷新率、动态元数据和eARC等新功能。这些功能使得消费者可以获得更好的观影、游戏和音频体验。总的来说，HDMI协议版本2.1的发布代表了高清晰度多媒体接口技术的飞速发展，为消费者带来了更好的音视频体验和更大的便利性。然而，需要注意的是，HDMI协议版本2.1规范中也提到了一些技术细节需要消费者和生产商注意。例如，由于新版本支持的分辨率和帧率更高，产品设计和制造方面需要更加注重性能和稳定性。此外，新规范中的一些新特性可能需要更新现有的硬件和软件，因此对于消费者和制造商来说，需要考虑兼容性和更新成本。总的来说，HDMI协议版本2.1的发布代表了高清晰度多媒体接口技术的最新进展，为消费者带来了更好的音视频体验。然而，对于消费者和制造商来说，需要在更新硬件和软件方面做出相应的考虑，以确保新技术的兼容性和稳定性。相信随着时间的推移，新规范会逐渐得到广泛接受，为消费者带来更好的产品和体验。

HDMI Forum Confidential Page 16 of 478

Figure 9-29: ERX_LATENCY_REQ Register Use Example ................................................................................................. 244

522

Figure 9-30: eARC example circuit depicting Differential Audio and Common Mode Data Channel Data ..................... 250

523

Figure 9-31: eARC Eye Diagram Mask at TP2, eARC Source for Audio data output ........................................................ 250

524

Figure 10-1: SCDC Update Read ...................................................................................................................................... 287

525

Figure 10-2: SCDC Combined Format Read ..................................................................................................................... 287

526

Figure 10-3: SCDC Write .................................................................................................................................................. 288

527

Figure 10-4: Read Request signal .................................................................................................................................... 290

528

Figure 10-5: Read Request signal with STOP condition................................................................................................... 291

529

Figure 10-6: Read Request Timeout ................................................................................................................................ 292

530

Figure 10-7: EDID Latency Handling for a Repeater with Video Processing .................................................................... 295

531

Figure 10-8: EDID Latency Handling for an Amplifier ...................................................................................................... 296

532

Figure 10-9: EDID Latency Handling for an Amplifier with Video Processing ................................................................. 297

533

Figure 10-10: Dynamic Auto Lipsync Example of Operation ........................................................................................... 299

534

Figure 10-11: Example of the use of [Low Latency Mode] flag ....................................................................................... 302

535

Figure 10-12: TV reports updated latency value(s) and flags when changing latency .................................................... 303

536

Figure 10-13: TV reports current latency value(s) and flags upon request ..................................................................... 303

537

Figure 10-14: Three-device scenario, initiation by Amplifier’s request .......................................................................... 304

538

Figure 10-15: Operation of audio delay when [Audio Output Compensated]=1 versus 2 .............................................. 305

539

Figure 10-16: Timing of the FAPA Relative to the Video Timing, FAPA_start_location=0 .............................................. 310

540

Figure 10-17: Timing of the FAPA Relative to the Video Timing, FAPA_start_location=1 .............................................. 311

541

Figure 10-18: Scope of Multi-Touch definition covered by This Specification ................................................................ 315

542

Figure 11-1: Logical Address Allocation (Clarified from H14b CEC Figure 8) ................................................................... 331

543

Figure 11-2: A typical scenario for a device waking up (transitions #1 and #2) .............................................................. 337

544

Figure 11-3: A typical scenario for a device waking up (transition #4) ........................................................................... 338

545

Figure 11-4: A typical scenario for the broadcast (system) Standby feature (from H14b CEC Figure 13) ...................... 338

546

Figure 11-5: A typical scenario for the Standby feature to a specific device (Clarified from H14b CEC Figure 14) ........ 339

547

Figure 11-6: A typical scenario where the user presses and quickly releases the same button (Clarified from H14b CEC

548

Figure 22) ........................................................................................................................................................................ 341

549

Figure 11-7: A typical scenario where the user quickly presses a second button ........................................................... 341

550

Figure 11-8: The messages sent in the Vendor Specific Commands feature (from H14b CEC Figure 21) ....................... 347

551

Figure 11-9: Example message flow, when a CEC Switch is manually switched (from H14b CEC Figure 12) .................. 352

552

Figure 11-10: An example of TV and Amplifier implementing Press and Hold behavior (Clarified from H14b CEC Figure

553

32) ................................................................................................................................................................................... 353

554

Figure 11-11: A Typical Operation of the volume control where the user presses and quickly releases a button ......... 354

555

Figure 11-12: An example of TV and STB implementing Press and Hold behavior ......................................................... 355

556

Figure 11-13: Typical Operation to discover the Audio Format capability of an Amplifier (Clarified from H14b CEC Figure

557

34) ................................................................................................................................................................................... 356

558

Figure 12-1: Standard Power Delivery Cases .................................................................................................................. 389

559

Figure 12-2: Power Delivery with a Repeater, Simple Cases ........................................................................................... 390

560

Figure 12-3: Power Delivery with a Repeater, Compound Cases .................................................................................... 390

561

Figure 12-4: Example of Possible Sink Device Cable Detach/Attach Detection .............................................................. 394

562

Figure 12-5: Initial Power Provisioning ........................................................................................................................... 395

563

Figure 12-6: Power Use Case: Source Operates as a PSink, Sink operates as a PSource ................................................ 397

564

Figure 12-7: Power Use Case: Source Operates as a PSource, Sink operates as a PSink ................................................ 398

565

Figure 12-8: Power Delivery State Machine for Sources Capable of functioning as a PSource ...................................... 400

566

Figure 12-9: AdDDC Channel Layers ................................................................................................................................ 445

567

HDMI Forum Confidential Page 17 of 478

Figure 12-10: AdDDC Electrical Circuitry ......................................................................................................................... 446

568

Figure 12-11: Differential AdDDC Signal Waveform from Source to Sink at TP1 without Backward Signal ................... 447

569

Figure 12-12: Differential AdDDC Signal Waveform from Sink to Source at TP2 without Forward Signal...................... 447

570

Figure 12-13: Differential AdDDC Signal Waveform at TP2 with Matching Waveform and Delay between Source and

571

Sink without Interconnection .......................................................................................................................................... 447

572

Figure 12-14: TP1 Input Eye Diagram for AdDDC Backward Signal ................................................................................. 450

573

Figure 12-15: AdDDC Reference Cable Equalizer Gain Curve .......................................................................................... 451

574

Figure 12-16: TP2 Input Eye Diagram for AdDDC Forward Signal ................................................................................... 454

575

Figure 12-17: Category 3 Cable DDC Attenuation Limits – Informative .......................................................................... 455

576

Figure 12-18: AdDDC State Diagram ............................................................................................................................... 457

577

Figure 12-19: TDM Structure ........................................................................................................................................... 459

578

Figure 12-20: TDM State Machine Example .................................................................................................................... 460

579

Figure 12-21: Slot 0 Transaction...................................................................................................................................... 462

580

Figure 12-22: Slot 0 Transport CRC Code Generator ....................................................................................................... 463

581

Figure 12-23: DDC vs. DDC Tunneling Transactions ........................................................................................................ 466

582

Figure 12-24: Slots 1…24 Channel ................................................................................................................................... 467

583

Figure 12-25: Transport Container Transaction .............................................................................................................. 468

584

Figure 12-26: Transport Container CRC Code Generator ................................................................................................ 469

585

Figure 12-27: Transport Container Credit Exchange Example ........................................................................................ 471

586

Figure 12-28: Transport Container structure .................................................................................................................. 472

587

Figure 12-29: Message Fragmentation Example ............................................................................................................. 474

588

Figure 12-30: Unfair Transport Container Buffer Usage Example ................................................................................... 475

589

Figure 12-31: Fair Transport Container Buffer Usage Example ....................................................................................... 476

590

Figure 12-32: Protocol Flow Control Example ................................................................................................................. 477

591

592

593

HDMI Forum Confidential Page 18 of 478

Table of Tables

594

Table 5-1: Type A with Power Connector Pin Assignment .................................................................................................42

595

Table 5-2: Type D with Power Connector Pin Assignment .................................................................................................42

596

Table 5-3: Connector Contact Sequence for Type A Connector .........................................................................................43

597

Table 5-4: Cable Assembly Parameters ..............................................................................................................................49

598

Table 5-5: Type A, Category 1, 2 vs. Category 3 Connector Pin Assignment Comparison .................................................52

599

Table 5-6: Type C, Category 1, 2 vs.to Category 3 Connector Pin Assignment Comparison ..............................................53

600

Table 5-7: Type D, Category 1, 2 vs. Category 3 Connector Pin Assignment Comparison .................................................53

601

Table 5-8: Electrical Performance ......................................................................................................................................55

602

Table 6-1: DC Characteristics for 3.4 Gbps < R

bit

≤ 6.0 Gbps at TP1 ...................................................................................61

603

Table 6-2: AC Characteristics for 3.4 Gbps < R

bit

≤ 6.0 Gbps at TP1 ...................................................................................61

604

Table 6-3: Source Impedance Characteristics for 3.4 Gbps < R

bit

≤ 6.0 Gbps at TP1 ..........................................................61

605

Table 6-4: HDMI Source Jitter Characteristics for 3.4 Gbps < R

bit

≤ 6.0 Gbps at TP2_EQ ...................................................62

606

Table 6-5: Functions defining horizontal and vertical dimensions for the eye diagram at TP2_EQ ..................................63

607

Table 6-6: Sink Operating DC Input Characteristics for devices supporting 3.4 Gbps < R

bit

≤ 6.0 Gbps at TP2 ..................64

608

Table 6-7: Sink AC Input Characteristics for 3.4 Gbps < R

bit

≤ 6.0 Gbps at TP2 ..................................................................64

609

Table 6-8: Sink Impedance Characteristics for 3.4 Gbps < R

bit

≤ 6.0 Gbps at TP2 ..............................................................64

610

Table 6-9: Summary of scrambling periods ........................................................................................................................66

611

Table 6-10: First 32 LFSR Values for all Data Channels ......................................................................................................68

612

Table 6-11: Bit assignments for XOR logic operation for 8-bit data ...................................................................................69

613

Table 6-12: Bit assignments for XOR logic operation for 4-bit data ...................................................................................69

614

Table 6-13: 8-bit values that map to the TMDS Video Guard Band Codes ........................................................................69

615

Table 6-14: 8-bit values that map to the TMDS Data Island Guard Band Codes ................................................................69

616

Table 6-15: IToggle Bit Generation Variables .....................................................................................................................71

617

Table 6-16: Bit assignments for XOR logic operation for 4-bit data ...................................................................................72

618

Table 6-17: 10-bit codes for scrambled control periods ....................................................................................................72

619

Table 6-18: CEC line Electrical Specifications for all Configurations ..................................................................................84

620

Table 6-19: FRL Lane link rates ...........................................................................................................................................86

621

Table 6-20: DC Characteristics for 6 Gbps, 8 Gbps, 10 Gbps, and 12 Gbps at TP1 .............................................................88

622

Table 6-21: AC Characteristics for 3 Gbps, 6 Gbps, 8 Gbps, 10 Gbps, and 12 Gbps at TP1 ................................................89

623

Table 6-22: Source Impedance Characteristics for 3 Gbps, 6 Gbps, 8 Gbps, 10 Gbps, and 12 Gbps at TP1 (Informative) 89

624

Table 6-23: Parameters defining horizontal and vertical dimensions for the 16b18b eye diagram at TP2_EQ ................90

625

Table 6-24: TP2_EQ Source Jitter Requirement (unit is T

bit

= 1/R

bit

) ..................................................................................90

626

Table 6-25: Sink operating DC Input Characteristics for Devices supporting 3 Gbps, 6 Gbps, 8 Gbps, 10 Gbps, and 12

627

Gbps at TP2 ........................................................................................................................................................................91

628

Table 6-26: Sink AC Input Characteristics for 3 Gbps, 6 Gbps, 8 Gbps, 10 Gbps, and 12 Gbps at TP2 ...............................91

629

Table 6-27: Sink Impedance Characteristics for 3 Gbps, 6.0 Gbps, 8 Gbps, 10 Gbps, 12 Gbps at TP2 (Informative) .........91

630

Table 6-28: P2_EQ Sink Jitter Tolerance Requirement (unit is T

bit

= 1/R

bit

)........................................................................92

631

Table 6-29: Sinusoidal Jitter Frequency and Jitter Amplitude for Sink Jitter Tolerance Test .............................................92

632

Table 6-30: HF-VSDB registers for Sink Link Training Capability ........................................................................................93

633

Table 6-31: SCDC registers for Link Training ......................................................................................................................93

634

Table 6-32: Link Training Patterns in 16b18b mode ..........................................................................................................94

635

Table 6-33: First 11 LFSR values for 16b18b PRBS .............................................................................................................95

636

Table 6-34: Link Training States .........................................................................................................................................96

637

Table 6-35: FRL Map Character – FRL Packet Type ......................................................................................................... 100

638

HDMI Forum Confidential Page 19 of 478

Table 6-36: Video Guard Band symbols and TMDS-decoded symbols for the TMDS Data Channels ............................. 101

639

Table 6-37: Mapping Video Blanking Data (Control Period, Island Guard Bands, and Island Data) to FRL Characters .. 113

640

Table 6-38: Conditions for FRL Examples ....................................................................................................................... 135

641

Table 6-39: Compute Parameters based on the Source Video ....................................................................................... 136

642

Table 6-40: Compute Bit Rate related Items ................................................................................................................... 136

643

Table 6-41: Active Video Period Infrastructure ............................................................................................................... 136

644

Table 6-42: Video Blank Period Infrastructure ................................................................................................................ 137

645

Table 6-43: Pixel Format Computations .......................................................................................................................... 138

646

Table 6-44: Video Pixel Results ....................................................................................................................................... 138

647

Table 6-45: Audio Support Verification Computations ................................................................................................... 139

648

Table 6-46: Additional Computations for Compressed Video ......................................................................................... 139

649

Table 6-47: Encoding of FRL Packet Characters .............................................................................................................. 141

650

Table 6-48: FRL Special Characters .................................................................................................................................. 142

651

Table 6-49: First 16 LFSR Values for all Data Lanes with 16b18b Coding ........................................................................ 143

652

Table 6-50: Bit assignments for XOR logic operation for 16-bit data .............................................................................. 144

653

Table 7-1: Video Timings that may be used with YC

4:2:0 Pixel Encoding ................................................................. 145

654

Table 7-2: Mapping Two 8-bit per component 4:2:0 Pixels to one 24-bit 4:4:4 Pixel prior to Deep Color Packing ........ 148

655

Table 7-3: Mapping Two 10-bit per component 4:2:0 Pixels to one 30-bit 4:4:4 Pixel prior to Deep Color Packing ...... 148

656

Table 7-4: Mapping Two 12-bit per component 4:2:0 Pixels to one 36-bit 4:4:4 Pixel prior to Deep Color Packing ...... 149

657

Table 7-5: Mapping Two 16-bit per component 4:2:0 Pixels to one 48-bit 4:4:4 Pixel prior to Deep Color Packing ...... 149

658

Table 7-6: Video Formats defined in ITU-R BT.2020 that are supported by This Specification ...................................... 151

659

Table 7-7: Video Quantization signaling (values for Q1, Q0) for RGB encoding ............................................................. 152

660

Table 7-8: Video Quantization signaling (values for YQ1 and YQ0) for YC

Pixel Encoding ......................................... 152

661

Table 7-9: 3D_Disparity_Data for 3D_DisparityData_version=001 ................................................................................. 153

662

Table 7-10: 3D_Disparity_Data for 3D_DisparityData_version=010 ............................................................................... 154

663

Table 7-11: Definition and values of multi_region_disparity_length and 3D_DisparityData_length ............................. 154

664

Table 7-12: Computing FVA_FACTOR

MAX

......................................................................................................................... 158

665

Table 7-13: VRRFVA Extended Metadata Structure ........................................................................................................ 160

666

Table 7-14: Nominal Recommended bpp Settings .......................................................................................................... 166

667

Table 7-15: Extended Recommended bpp Settings ........................................................................................................ 167

668

Table 7-16: VESA DSC PPS Summary ............................................................................................................................... 169

669

Table 7-17: VESA DSC rc parameter set summary .......................................................................................................... 170

670

Table 7-18: Example VESA DSC PPS Element “slice_width” computation results........................................................... 172

671

Table 7-19: Sample Results for 3 Lane applications ........................................................................................................ 174

672

Table 7-20: Sample Results for 4 Lane applications ........................................................................................................ 174

673

Table 7-21: Determining Max Supportable Audio Rate .................................................................................................. 175

674

Table 8-1: Packet Types ................................................................................................................................................... 178

675

Table 8-2: 3D Audio Sample Packet Header .................................................................................................................... 179

676

Table 8-3: One Bit 3D Audio Packet Header .................................................................................................................... 180

677

Table 8-4: Audio Metadata Packet Header ..................................................................................................................... 181

678

Table 8-5: Valid Bit Configurations for Audio Metadata Header .................................................................................... 183

679

Table 8-6: Audio Metadata Packet contents for 3D_AUDIO=1 ....................................................................................... 184

680

Table 8-7: 3D_CC field ..................................................................................................................................................... 185

681

Table 8-8: Audio Channel Allocation Standard Type field ............................................................................................... 185

682

Table 8-9: 3D_CA field for 10.2 Channels

(1)

(ACAT = 0x01) ............................................................................................. 186

683

Table 8-10: 3D_CA field for 22.2 Channels

(2)

(ACAT = 0x02) (Part 1 of 2) ........................................................................ 186

684

HDMI Forum Confidential Page 20 of 478

Table 8-11: 3D_CA field for 30.2 Channels

(3)

(ACAT = 0x03) (Part 1 of 3) ....................................................................... 187

685

Table 8-12: Audio Metadata Packet contents when 3D_Audio=0 and CTA_3D_AUDIO=0 ............................................. 189

686

Table 8-13: Audio Metadata Descriptor .......................................................................................................................... 189

687

Table 8-14: Supplementary Audio Type .......................................................................................................................... 191

688

Table 8-15: Multi-Stream Audio Sample Packet Header ................................................................................................. 192

689

Table 8-16: One Bit Multi-Stream Audio Packet Header ................................................................................................. 193

690

Table 8-17: Extended Metadata Packet Header ............................................................................................................. 195

691

Table 8-18: Extended Metadata Packet Contents for Sequence_Index=0, First=1 ......................................................... 196

692

Table 8-19: Extended Metadata Packet Contents when First is cleared (=0) ................................................................. 199

693

Table 9-1: Operand Description of [Audio Format ID and Code] .................................................................................... 200

694

Table 9-2: Allowed Values for Channel Status bits 24 to 27, 30, and 31 ......................................................................... 201

695

Table 9-3: Supported Sample Frequency or Frame Rate for each Packet Type .............................................................. 202

696

Table 9-4: Recommended N and expected CTS for Audio Sample Frequency or Frame Rate of 32 kHz and

697

Multiples thereof ............................................................................................................................................................ 204

698

Table 9-5: Recommended N and expected CTS for Audio Sample Frequency or Frame Rate of 44.1 kHz and

699

multiples thereof ............................................................................................................................................................. 205

700

Table 9-6: Recommended N and expected CTS for Audio Sample Frequency or Frame Rate of 48 kHz and

701

multiples thereof ............................................................................................................................................................. 206

702

Table 9-7: Max 3D Audio Sampling Frequencies for 24-bit Video Format Timings (Informative) .................................. 208

703

Table 9-8: Max 3D Audio Sampling Frequencies for 24-bit 4:2:0 Video Format Timings (Informative) ......................... 209

704

Table 9-9: Channel Mapping for 12 Channel 3D Audio Sample Packet ........................................................................... 210

705

Table 9-10: Channel Mapping for 24 Channel 3D Audio Sample Packet......................................................................... 210

706

Table 9-11: Channel Mapping for 32-Channel 3D Audio Sample Packet ........................................................................ 210

707

Table 9-12: Valid Sample_Present Bit Configurations for 3D Audio ............................................................................... 211

708

Table 9-13: Mapping for Multi-Stream Audio Sample Packet with 2 audio streams ...................................................... 214

709

Table 9-14: mapping for Multi-Stream Audio Sample Packet with 3 audio streams ...................................................... 214

710

Table 9-15: Mapping for Multi-Stream Audio Sample Packet with 4 audio streams ...................................................... 214

711

Table 9-16: Valid Stream_Present Bit Configurations for Multi-Stream Audio transmission ......................................... 215

712

Table 9-17: eARC Naming Convention ............................................................................................................................ 218

713

A comparison of SPDIF, ARC, and eARC has been provided in Table 9-18.Table 9-18: eARC Audio Electrical Parameters

714

......................................................................................................................................................................................... 222

715

Table 9-19: Audio Packet Layout and Layout Value ........................................................................................................ 224

716

Table 9-20: Discovery and Disconnection Timing ........................................................................................................... 232

717

Table 9-21: eARC Common Mode Data Channel Timings ............................................................................................... 235

718

Table 9-22: eARC Common Mode Data Channel Commands ......................................................................................... 236

719

Table 9-23: eARC Common Mode Data Channel Device IDs ........................................................................................... 237

720

Table 9-24: Summary of Command or Data Packets for eARC Transaction Types.......................................................... 240

721

Table 9-25: eARC RX and Source Status Registers........................................................................................................... 241

722

Table 9-26: eARC Latency Registers ................................................................................................................................ 243

723

Table 9-27: eARC Capabilities and Status Data Structure ............................................................................................... 247

724

Table 9-28: Capabilities and Status Block ........................................................................................................................ 247

725

Table 9-29: BLOCK_ID Values .......................................................................................................................................... 247

726

Table 9-30: Type A Connector Pin Assignment................................................................................................................ 249

727

Table 9-31: Differential Mode Electrical Specifications .................................................................................................. 251

728

Table 9-32: Common Mode Data Channel Electrical Specifications ............................................................................... 251

729

Table 9-33: Cable Assembly Electrical Specifications (from H14b HEAC Table 2-17) ...................................................... 252

730

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