Altera FPGA外部存储器接口设计手册

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"Altera外部存储器接口参考是针对 Altera FPGA 的一个重要手册，主要针对DDR、DDR2和DDR3等内存类型的开发提供指导。该手册由Altera公司发布，适用于13.1版本的设计套件。内容涵盖Altera内存解决方案的概述、设计流程、协议支持矩阵以及未来Arria 10 EMI的协议支持等。此外，还提供了设计检查清单，以帮助开发者按照推荐的设计流程进行工作。" Altera的内存解决方案介绍: Altera提供的外部存储器接口IP核心是业界最快、效率最高且延迟最低的解决方案。这些IP核旨在轻松对接当前高速内存设备，确保在处理高带宽需求时能实现最优性能。Altera支持多种内存接口，适用于各种应用，从路由器、网络设备到高性能计算系统，都能找到适合的内存接口方案。协议支持矩阵: 该矩阵详细列出了Altera IP对不同内存标准的支持情况，包括DDR、DDR2和DDR3等，这有助于开发者根据项目需求选择最适合的内存类型。对于高级应用，如Arria 10 EMI，手册还前瞻性地介绍了未来可能支持的新协议。设计流程: 推荐的设计流程包括一系列步骤，从初期的选择合适的内存类型，到配置IP核，再到综合、布局布线和仿真验证。设计检查清单提供了每个阶段的关键任务，确保开发者遵循最佳实践，减少错误和优化设计效率。文档修订历史: 手册包含了详细的修订历史，记录了每次更新的内容，这对于跟踪技术发展和保持设计方案的最新状态至关重要。综上，"Altera外部存储器接口参考"是开发者进行FPGA内存设计的重要参考资料，它提供了全面的指导，包括设计策略、协议选择、优化技巧等，帮助开发者充分利用Altera FPGA的内存接口能力，实现高效、可靠的系统设计。

External Memory Interface Handbook

Volume 2: Design Guidelines

Last updated for Altera Complete Design Suite: 13.1 A10

101 Innovation Drive

San Jose, CA 95134

www.altera.com

EMI_DG

2013.12.16

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Contents

Selecting Your Memory.......................................................................................1-1

DDR SDRAM Features...............................................................................................................................1-2

DDR2 SDRAM Features.............................................................................................................................1-2

DDR3 SDRAM Features.............................................................................................................................1-2

QDR, QDR II, and QDR II+ SRAM Features..........................................................................................1-3

RLDRAM II and RLDRAM 3 Features.....................................................................................................1-4

LPDDR2 Features........................................................................................................................................1-5

Memory Selection........................................................................................................................................1-6

Example of High-Speed Memory in Embedded Processor....................................................................1-8

Example of High-Speed Memory in Telecom..........................................................................................1-9

Document Revision History.....................................................................................................................1-11

Selecting Your FPGA Device...............................................................................2-1

Memory Standards.......................................................................................................................................2-1

I/O Interfaces................................................................................................................................................2-2

Wraparound Interfaces...............................................................................................................................2-2

Read and Write Leveling.............................................................................................................................2-2

Dynamic OCT..............................................................................................................................................2-2

Device Settings Selection.............................................................................................................................2-3

Device Speed Grade.........................................................................................................................2-3

Device Operating Temperature.....................................................................................................2-3

Device Package Size.........................................................................................................................2-3

Device Density and I/O Pin Counts..............................................................................................2-3

Document Revision History.......................................................................................................................2-5

Planning Pin and FPGA Resources.....................................................................3-1

Interface Pins................................................................................................................................................3-1

Estimating Pin requirements..........................................................................................................3-4

DDR, DDR2, and DDR3 SDRAM Clock Signals........................................................................3-4

DDR, DDR2, and DDR3 SDRAM Command and Address Signals.........................................3-5

DDR, DDR2, and DDR3 SDRAM Data, Data Strobes, DM, and Optional ECC

Signals..........................................................................................................................................3-5

DDR, DDR2, and DDR3 SDRAM DIMM Options....................................................................3-6

Altera Corporation

External Memory Interface Handbook Volume 2: Design Guidelines

TOC-2

QDR II+ and QDR II SRAM Clock Signals.................................................................................3-9

QDR II+ and QDR II SRAM Command Signals.........................................................................3-9

QDR II+ and QDR II SRAM Address Signals.............................................................................3-9

QDR II+ and QDR II SRAM Data and QVLD Signals...............................................................3-9

RLDRAM II and RLDRAM 3 Clock Signals..............................................................................3-10

RLDRAM II and RLDRAM 3 Commands and Addresses.......................................................3-11

RLDRAM II and RLDRAM 3 Data, DM and QVLD Signals..................................................3-11

LPDDR2 Clock Signal...................................................................................................................3-12

LPDDR2 Command and Address Signal...................................................................................3-13

LPDDR2 Data, Data Strobe, and DM Signals............................................................................3-13

Maximum Number of Interfaces.................................................................................................3-13

OCT Support for Arria II GX, Arria II GZ, Arria V, Arria V GZ, Cyclone V, Stratix III,

Stratix IV, and Stratix V Devices............................................................................................3-24

General Pin-out Guidelines......................................................................................................................3-25

Arria 10 Pin Placement Rules and Guidelines.......................................................................................3-27

Arria 10 Pin Placement Rules and Guidelines: Interface-Level ..............................................3-27

Arria 10 Pin Placement Rules and Guidelines: Address/Command Pins .............................3-28

Arria 10 Pin Placement Rules and Guidelines: Data Pins .......................................................3-28

Arria 10 Pin Placement Rules and Guidelines: Other Pins .....................................................3-28

Pin-out Rule Exceptions for ×36 Emulated QDR II and QDR II+ SRAM Interfaces in Arria II,

Stratix III and Stratix IV Devices.......................................................................................................3-28

Timing Impact on x36 Emulation...............................................................................................3-30

Rules to Combine Groups............................................................................................................3-31

Determining the CQ/CQn Arrival Time Skew..........................................................................3-31

Pin-out Rule Exceptions for RLDRAM II and RLDRAM 3 Interfaces..............................................3-33

Interfacing with ×9 RLDRAM II CIO Devices..........................................................................3-33

Interfacing with ×18 RLDRAM II and RLDRAM 3 CIO Devices..........................................3-34

Interfacing with RLDRAM II and RLDRAM 3 ×36 CIO Devices..........................................3-34

Pin-out Rule Exceptions for QDR II and QDR II+ SRAM Burst-length-of-two Interfaces...........3-35

Pin Connection Guidelines Tables..........................................................................................................3-36

DDR3 SDRAM With Leveling Interface Pin Utilization Applicable for Arria V GZ, Stratix

III, Stratix IV, and Stratix V Devices.....................................................................................3-37

QDR II and QDR II+ SRAM Pin Utilization for Arria II, Arria V, Stratix III, Stratix IV,

and Stratix V Devices...............................................................................................................3-39

RLDRAM II CIO Pin Utilization for Arria II GZ, Arria V, Stratix III, Stratix IV, and

Stratix V Devices .....................................................................................................................3-40

LPDDR2 Pin Utilization for Arria V, Cyclone V, and Stratix V Devices..............................3-41

Additional Guidelines for Arria V GZ and Stratix V Devices.................................................3-42

Additional Guidelines for Arria V ( Except Arria V GZ) Devices..........................................3-44

Altera Corporation

TOC-3

External Memory Interface Handbook Volume 2: Design Guidelines

Additional Guidelines for Cyclone V Devices...........................................................................3-45

PLLs and Clock Networks........................................................................................................................3-45

Number of PLLs Available in Altera Device Families..............................................................3-46

Number of Enhanced PLL Clock Outputs and Dedicated Clock Outputs Available in

Altera Device Families.............................................................................................................3-47

Number of Clock Networks Available in Altera Device Families...........................................3-47

Clock Network Usage in UniPHY-based Memory Interfaces—DDR2 and DDR3 SDRAM

(1) (2)

............................................................................................................................................3-48

Clock Network Usage in UniPHY-based Memory Interfaces—RLDRAM II, and QDR II

and QDR II+ SRAM.................................................................................................................3-49

PLL Usage for DDR, DDR2, and DDR3 SDRAM Without Leveling Interfaces...................3-49

PLL Usage for DDR3 SDRAM With Leveling Interfaces.........................................................3-50

Using PLL Guidelines................................................................................................................................3-51

PLL Cascading............................................................................................................................................3-51

DLL..............................................................................................................................................................3-52

Other FPGA Resources.............................................................................................................................3-53

Document Revision History.....................................................................................................................3-53

DDR2, DDR3, and DDR4 SDRAM Board Design Guidelines...........................4-1

Leveling and Dynamic ODT......................................................................................................................4-2

Read and Write Leveling.................................................................................................................4-2

Dynamic ODT..................................................................................................................................4-4

Dynamic OCT in Stratix III and Stratix IV Devices...................................................................4-5

Dynamic OCT in Stratix V Devices...............................................................................................4-6

Board Termination for DDR2 SDRAM....................................................................................................4-6

External Parallel Termination........................................................................................................4-6

On-Chip Termination.....................................................................................................................4-7

Recommended Termination Schemes..........................................................................................4-8

Dynamic On-Chip Termination..................................................................................................4-12

Board Termination for DDR3 SDRAM..................................................................................................4-13

Terminations for Single-Rank DDR3 SDRAM Unbuffered DIMM......................................4-14

Terminations for Stratix III, Stratix IV, and Stratix V FPGAs................................................4-16

Terminations for Multi-Rank DDR3 SDRAM Unbuffered DIMM.......................................4-17

Terminations for DDR3 SDRAM Registered DIMM...............................................................4-19

Terminations for DDR3 SDRAM Load-Reduced DIMM........................................................4-19

Terminations for DDR3 SDRAM Components With Leveling..............................................4-20

Drive Strength............................................................................................................................................4-22

How Strong is Strong Enough?....................................................................................................4-22

Altera Corporation

External Memory Interface Handbook Volume 2: Design Guidelines

TOC-4

System Loading..........................................................................................................................................4-23

Component Versus DIMM..........................................................................................................4-23

Single Versus DualRank DIMM..................................................................................................4-23

Single DIMM Versus Multiple DIMMs......................................................................................4-24

DDR3 and DDR4 on Arria 10 Devices...................................................................................................4-24

Dynamic On-Chip Termination (OCT) in Arria 10 Devices..................................................4-24

Dynamic On-Die Termination (ODT) in DDR4......................................................................4-25

Choosing Terminations on Arria 10 Devices............................................................................4-26

Design Layout Guidelines.........................................................................................................................4-26

General Layout Guidelines...........................................................................................................4-27

Layout Guidelines for DDR2 SDRAM Interface.......................................................................4-27

Layout Guidelines for DDR3 and DDR4 SDRAM Interfaces..................................................4-32

Length Matching Rules.................................................................................................................4-36

Layout Guidelines for DDR3 SDRAM Wide Interface (>72 bits)..........................................4-38

Package Deskew.............................................................................................................................4-40

Document Revision History.....................................................................................................................4-43

Dual-DIMM DDR2 and DDR3 SDRAM Board Design Guidelines..................5-1

General Layout Guidelines.........................................................................................................................5-1

Dual-Slot Unbuffered DDR2 SDRAM......................................................................................................5-2

Overview of ODT Control..............................................................................................................5-3

DIMM Configuration......................................................................................................................5-5

Dual-DIMM Memory Interface with Slot 1 Populated..............................................................5-5

Dual-DIMM with Slot 2 Populated...............................................................................................5-6

Dual-DIMM Memory Interface with Both Slot 1 and Slot 2 Populated..................................5-7

Dual-DIMM DDR2 Clock, Address, and Command Termination and Topology..............5-10

Address and Command Signals...................................................................................................5-10

Control Group Signals..................................................................................................................5-10

Clock Group Signals......................................................................................................................5-11

Dual-Slot Unbuffered DDR3 SDRAM....................................................................................................5-11

Comparison of DDR3 and DDR2 DQ and DQS ODT Features and Topology...................5-11

Dual-DIMM DDR3 Clock, Address, and Command Termination and Topology..............5-12

FPGA OCT Features......................................................................................................................5-12

Document Revision History.....................................................................................................................5-13

LPDDR2 SDRAM Board Design Guidelines......................................................6-1

LPDDR2 SDRAM Configurations.............................................................................................................6-1

OCT Signal Terminations for Arria V and Cyclone V Devices............................................................6-4

Altera Corporation

TOC-5

External Memory Interface Handbook Volume 2: Design Guidelines

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